Precharge circuitry for memory

A memory comprising:

• a plurality of memory cells arranged in columns and rows, each memory cell comprising an arrangement of memory cell transistors defining a first storage node and an inverted first storage node accessed from a first bit line and a second bit line;
• and
• at least one precharge circuit, wherein the precharge circuit is connected to the first bit line and the second bit line within a column, wherein each precharge circuit is configured to limit the first bit line to a first bit line precharge level and the second bit line to a second bit line precharge level during a precharge cycle,
• wherein the precharge circuit comprises a PMOS transistor based or NMOS transistor based precharge portion configured to precharge the first bit line and the second bit line;
• and a PMOS transistor based or NMOS transistor based limiting portion configured to limit the first bit line precharge level and the second bit line precharge level relative to a supply voltage (VDD) or ground reference level (GND) without substantial delay by short-circuiting the first bit line to a first limited precharge level node of the PMOS transistor based or NMOS transistor based limiting portion, and by short-circuiting the second bit line to a second limited precharge level node of the PMOS transistor based or NMOS transistor based limiting portion.

A precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising:

• a precharge and limiting unit configured to precharge a first bit line and a second bit line, the precharge and limiting unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and/or write operation of any of the memory cells,
• wherein the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay,
• wherein the precharge circuitry comprises:
• a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, the first, second, and third PMOS transistors being connected in series to provide a precharge portion;
• a fourth PMOS transistor and a fifth PMOS transistor connected between the precharge portion and a supply voltage (VDD) to provide a limiting portion,
• wherein the first bit line is connected to either a fourth gate terminal of the fourth PMOS transistor or to a second gate terminal of the second PMOS transistor, thereby limiting the first bit line precharge level, and
• wherein the second bit line is connected to either a fifth gate terminal of the fifth PMOS transistor or to a third gate terminal of the third PMOS transistor, thereby limiting the second bit line precharge level.

A precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising:

• a precharge and limiting unit configured to precharge a first bit line and a second bit line, the precharge and limiting unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and/or write operation of any of the memory cells,
• wherein the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay,
• wherein the precharge circuitry comprises:
• a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, the first, second, and third NMOS transistors being connected in series to provide a precharge portion;
• a fourth NMOS transistor and a fifth NMOS transistor connected between the precharge portion and a ground reference point (GND) to provide a limiting portion relative to the ground reference point,
• wherein the first bit line is connected to either a fourth gate terminal of the fourth NMOS transistor or to a second gate terminal of the second NMOS transistor, thereby limiting the first bit line precharge level relative to the ground reference point, and
• wherein the second bit line is connected to either a fifth gate terminal of the fifth NMOS transistor or to a third gate terminal of the third NMOS transistor, thereby limiting the second bit line precharge level relative to the ground reference point.

A precharge circuitry for bit lines of an array of memory cells, the precharge circuitry comprising:

• a precharge and limiting unit configured to precharge a first bit line and a second bit line, the precharge and limiting unit further configured to limit a first bit line precharge level of the first bit line and a second bit line precharge level of the second bit line during a precharge cycle of a read and/or write operation of any of the memory cells,
• wherein the precharge and limiting unit is configured to limit the first bit line precharge level and the second bit line precharge level in a single precharge cycle, preferably without substantial delay,
• wherein the precharge circuitry comprises:
• a first NMOS transistor having a first gate terminal, a first drain terminal, and a first source terminal;
• a second NMOS transistor having a second gate terminal, a second drain terminal, and a second source terminal;
• and a third NMOS transistor having a third gate terminal, a third drain terminal, and a third source terminal,
• wherein a connection between the first and second NMOS transistors defines a first bit line node connected to the first bit line,
• wherein a connection between the first and third NMOS transistors defines a second bit line node connected to the second bit line, and
• wherein a precharge signal is connected to the first gate terminal, to the second gate terminal, and to the third gate terminal,
• wherein said first, second, and third NMOS transistors are dimensioned such that the first bit line precharge level and the second bit line precharge level are limited compared to a supply voltage, wherein the first bit line precharge level and the second bit line precharge level are 10-80% lower than the supply voltage.