US 12,373,661 B2 · Vectorized interleave of bit planes

Abstract

A bit plane converter and associated methods. In an embodiment, the bit plane converter is configured to receive a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels. The bit plane converter is configured to perform an interleave process on the pixels to generate bit fields for the pixels by processing low nibbles of a low-order word and the low nibbles of a higher-order word using a lookup table to generate a bitwise interleaved low nibble vector, processing high nibbles of the low-order word and the high nibbles of the higher-order word using the lookup table to generate a bitwise interleaved high nibble vector, and interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector.

Claims20

Dependent claims

A bit plane converter, comprising:

at least one processor;
and
a memory including computer program code executable by the processor to cause the bit plane converter at least to:
receive a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels;
and
perform an interleave process on the pixels to generate bit fields for the pixels, wherein the interleave process comprises:
processing low nibbles of a low-order word of the low-order bits and the low nibbles of a higher-order word of the higher-order bits using at least one lookup table to generate a bitwise interleaved low nibble vector;
processing high nibbles of the low-order word and the high nibbles of the higher-order word using the at least one lookup table to generate a bitwise interleaved high nibble vector;
and
interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector comprising the bit fields.

7 more elements

A method of converting bit planes into a bit field data structure, the method comprising:

receiving a first bit plane comprising low-order bits for an array of pixels, and a second bit plane comprising higher-order bits for the pixels;
and
performing an interleave process on the pixels to generate bit fields for the pixels by:
processing low nibbles of a low-order word of the low-order bits and the low nibbles of a higher-order word of the higher-order bits using at least one lookup table to generate a bitwise interleaved low nibble vector;
processing high nibbles of the low-order word and the high nibbles of the higher-order word using the at least one lookup table to generate a bitwise interleaved high nibble vector;
and
interleaving bytes of the bitwise interleaved low nibble vector with bytes of the bitwise interleaved high nibble vector to generate a bitwise interleaved vector comprising the bit fields.

4 more elements

Dependencies are inferred from the claim text.

Vectorized interleave of bit planes

Life of this patent

Vectorized interleave of bit planes

Life of this patent

Abstract

Claims20