Atomic handling for disaggregated 3D structured SoCs

A data processing system comprising:

• a system interconnect to facilitate communication with a host processor device, the host processor device coupled with a host memory;
• and
• a system on a chip integrated circuit (SoC) coupled with the system interconnect, the SoC including:
• an active base die including a first cache memory;
• a first die mounted on and coupled with the active base die, the first die including an interconnect fabric, an input/output interface, an atomic operation handler, and a memory interface to a device memory;
• and
• a second die mounted on the active base die and coupled with the active base die and the first die, the second die including an array of graphics processing elements and an interface to the first cache memory of the active base die, wherein at least one of the graphics processing elements are configured to perform, via the atomic operation handler, a first atomic operation to the host memory and a second atomic operation to the device memory, wherein the host memory is accessible via the input/output interface, a second cache memory is configured to cache data associated with the first atomic operation, and the second cache memory is associated with a burst buffer cache that is enabled when a rate of incoming atomic requests exceeds a burst rate threshold.