Layout pattern of semiconductor varactor and forming method thereof
AssigneeUnited Microelectronics Corp.
InventorsChing-Wen Hung, Peng-Hsiu Chen, Su-Ming Hsieh, Ying-Ren Chen
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Abstract
The invention provides a layout pattern of a semiconductor varactor, which comprises a plurality of varactor units arranged on a substrate, wherein each varactor unit comprises a plurality of fin structures arranged in parallel with each other, a plurality of gate structures arranged in parallel with each other, located on the substrate and spanning the fin structures, and a gate metal layer electrically connected with the plurality of gate structures.
Claims16
A layout pattern of a semiconductor varactor, comprising:
- a plurality of varactor units are arranged on a substrate, wherein each varactor unit comprising:
- a plurality of fin structures which are arranged in parallel with each other;
- a plurality of first gate structures arranged in parallel with each other, located on the substrate and spanning the plurality of fin structures;
- and
- a gate metal layer electrically connected to the plurality of first gate structures;
- and
- at least one well pickup structure located next to the varactor units, wherein the well pickup structure includes a plurality of second gate structures, wherein a length of the second gate structures is smaller than a length of the first gate structures in the varactor unit.
A method for manufacturing a layout pattern of a semiconductor varactor, comprising:
- forming a plurality of varactor units which are arranged on a substrate, wherein each varactor unit comprising:
- a plurality of fin structures which are arranged in parallel with each other;
- a plurality of first gate structures arranged in parallel with each other, located on the substrate and spanning the plurality of fin structures;
- a gate metal layer electrically connected to the first gate structures;
- and
- forming at least one well pickup structure located next to the varactor units, wherein the well pickup structure includes a plurality of second gate structures, wherein a length of the second gate structures is smaller than a length of the first gate structures in the varactor unit.
Dependencies are inferred from the claim text.