Capacitor devices with shared electrode and methods of fabrication

A device, comprising:

• a conductive interconnect in a first dielectric within a first level, the conductive interconnect comprising a first length along a first direction;
• a second level above the first level, the second level comprising:
• a plurality of electrode structures, wherein individual ones of the plurality of electrode structures are laterally spaced apart on the conductive interconnect along the first length, the individual ones of the plurality of electrode structures comprising a first conductive hydrogen barrier material;
• and
• an etch stop layer laterally surrounding the individual ones of the plurality of electrode structures, wherein the etch stop layer is on the conductive interconnect and on the first dielectric;
• a third level above the second level, the third level comprising a plurality of plate electrodes, wherein individual ones of the plurality of plate electrodes are on individual ones of the plurality of electrode structures, wherein the individual ones of the plurality of plate electrodes have a length that extend along a second direction orthogonal to the first direction;
• and
• a fourth level above the third level, the fourth level comprising:
• a plurality of memory devices, wherein a first individual ones of the plurality of memory devices are on a first individual one of the plurality of plate electrodes, wherein an individual memory device is on a second individual one of the plurality of plate electrodes, and wherein a second individual ones of the plurality of memory devices are on a third individual one of the plurality of plate electrodes;
• an encapsulation layer on sidewalls of the first individual ones of the plurality of memory devices, on the first individual one of the plurality of plate electrodes, on sidewall of the individual memory device, on sidewalls of the second individual ones of the plurality of memory devices and on the third individual one of the plurality of plate electrodes, wherein the encapsulation layer is substantially aligned with sidewalls of the first individual one of the plurality of plate electrodes, with the second individual one of the plurality of plate electrodes, and with the third individual one of the plurality of plate electrodes;
• a second dielectric on the encapsulation layer;
• and
• a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on the individual ones of the plurality of memory devices, and wherein the individual ones of the plurality of via electrodes comprise a second conductive hydrogen barrier material.

A system, comprising:

• a transistor comprising a source, gate and a drain;
• a device structure coupled with the gate or the drain of the transistor, the device structure comprising:
• a conductive interconnect in a first dielectric within a first level, the conductive interconnect comprising a first length along a first direction;
• a second level above the first level, the second level comprising:
• a plurality of electrode structures, wherein individual ones of the plurality of electrode structures are laterally spaced apart on the conductive interconnect along the first length, the individual ones of the plurality of electrode structures comprising a first conductive hydrogen barrier material, wherein an etch stop layer is laterally surrounding the individual ones of the plurality of electrode structures, and wherein the etch stop layer is on the conductive interconnect and on the first dielectric;
• a third level above the second level, the third level comprising a plurality of plate electrodes, wherein individual ones of the plurality of plate electrodes are on individual ones of the plurality of electrode structures and on a portion of the etch stop layer, and wherein the individual ones of the plurality of plate electrodes have a length that extend along a second direction orthogonal to the first direction;
• a fourth level above the third level, the fourth level comprising:
• a plurality of memory devices, wherein a first individual ones of the plurality of memory devices are on a first individual one of the plurality of plate electrodes, wherein an individual memory device is on a second individual one of the plurality of plate electrodes, and wherein a second individual ones of the plurality of memory devices are on a third individual one of the plurality of plate electrodes;
• an encapsulation layer on sidewalls of the first individual ones of the plurality of memory devices, on the first individual one of the plurality of plate electrodes, on sidewall of the individual memory device, on the first individual one of the plurality of plate electrodes, on sidewalls of the second individual ones of the plurality of memory devices and on the third individual one of the plurality of plate electrodes, wherein the encapsulation layer is substantially aligned with sidewalls of the first individual one of the plurality of plate electrodes, with the first individual one of the plurality of plate electrodes, and with the third individual one of the plurality of plate electrodes;
• a second dielectric on the encapsulation layer;
• a plurality of via electrodes wherein, individual ones of the plurality of via electrodes are on the individual ones of the plurality of memory devices, wherein individual ones of the plurality of via electrodes comprise a second conductive hydrogen barrier material;
• and a via structure coupled between the transistor and the conductive interconnect.