Low power clock network
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo Chun Lu, Shao-Yu Wang
Life of this patent
Estimating the term…
Abstract
A first clock signal is generated from a reference clock signal. A first frequency associated with the first clock signal is less than a reference clock frequency associated with the reference clock signal. The first clock signal is propagated towards a first component of an integrated circuit through a clock tree. A second clock signal having a second frequency is generated from the first clock signal at a terminal point of the clock tree. The second clock signal is provided to the first component.
Claims20
An integrated circuit, comprising:
- a reduction circuit operative to:
- receive a reference clock signal,
- generate a first clock signal from the received reference clock signal, and
- propagate the first clock signal to a leaf branch of a clock tree;
- and
- a combination circuit connected to the leaf branch of the clock tree, the combination circuit being operative to:
- receive the first clock signal from the leaf branch, and
- generate a second clock signal from the first clock signal, wherein the second clock signal has substantially the same frequency as that of the reference clock signal.
An integrated circuit, comprising:
- a reduction circuit operative to:
- receive a reference clock signal,
- reduce a reference clock frequency of the reference clock signal to generate a first clock signal, and
- propagate the first clock signal to a leaf branch to a clock tree;
- and
- a combination circuit connected to the leaf branch of the clock tree, wherein the combination circuit is operative to:
- receive the first clock signal from the leaf branch,
- generate a second clock signal from the first clock signal, and
- combine the first clock signal and the second clock signal to generate a third clock signal, wherein a frequency of the third clock signal is same as the reference clock frequency.
The integrated circuit of claim of 10, wherein the reference clock frequency is reduced by dividing the reference clock frequency by a factor of two.
An integrated circuit comprising:
- a clock tree comprising a plurality of leaf branches;
- a plurality of components connected to the plurality of leaf branches of the clock tree;
- and
- a clock circuit operative to:
- receive a reference clock signal,
- generate a first clock signal from the reference clock signal, wherein a first clock frequency of the first clock signal is less than a reference clock frequency of the reference clock signal,
- propagate the first clock signal through the clock tree towards the plurality of components,
- generate a second clock signal from the first clock signal, and
- provide the second clock signal to a first component of the plurality of components.
Dependencies are inferred from the claim text.