Logarithmic amplifiers in silicon microphones
AssigneeInfineon Technologies AG
InventorsJose Luis Ceballos, Fulvio CiCiotti, Dietmar Straeussnigg, Andreas Wiesbauer
Life of this patent
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Abstract
A logarithmic amplifier includes programmable gain amplifiers each having a different gain, wherein an input of each of the programmable gain amplifiers is coupled to an input of the logarithmic amplifier; and a summing circuit having inputs coupled to a corresponding output of each of the programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit generates a logarithmic transfer function having piecewise linear segments.
Claims20
A logarithmic amplifier comprising:
- a plurality of programmable gain amplifiers each having a different gain, wherein an input of each of the plurality of programmable gain amplifiers is coupled to an input of the logarithmic amplifier;
- and
- a summing circuit having a plurality of inputs coupled to a corresponding output of each of the plurality of programmable gain amplifiers and an output coupled to an output of the logarithmic amplifier, wherein the summing circuit is configured for generating a plurality of piecewise linear segments, wherein the summing circuit comprises a switched capacitor circuit.
A circuit comprising:
- a piecewise linear amplifier comprising a plurality of programmable gain amplifiers, the piecewise linear amplifier having an input for receiving an analog input voltage;
- an analog-to-digital converter (ADC) having an input coupled to an output of the piecewise linear amplifier;
- and
- a digital anti-logarithmic component coupled to an output of the ADC, wherein an output of the digital anti-logarithmic component provides a linearized digital signal corresponding to the analog input voltage.
A method comprising:
- amplifying an analog input signal in a plurality of parallel gain paths, wherein each of the parallel gain paths comprises a different gain value;
- generating a plurality of charges from a plurality of output voltages of the parallel gain paths, wherein generating the plurality of charges comprises generating the plurality of charges in a switched capacitor circuit;
- and
- summing the plurality of currents or charges to provide a piecewise linear output voltage approximating a logarithmic output voltage.
A circuit comprising:
- a plurality of programmable gain amplifiers each having a different gain, wherein an input of each of the plurality of programmable gain amplifiers is coupled to an input of the circuit;
- a summing circuit having a plurality of inputs coupled to a corresponding output of each of the plurality of programmable gain amplifiers and an output coupled to an output of the circuit, wherein the summing circuit is configured for generating a plurality of piecewise linear segments;
- and
- an anti-logarithmic component coupled to an output of the summing circuit, wherein an output of the anti-logarithmic component provides a linearized signal corresponding to an analog input signal at the input of the circuit.
Dependencies are inferred from the claim text.