Semiconductor packages

A semiconductor package, comprising:

• a package substrate;
• a redistribution substrate on the package substrate, the redistribution substrate including a plurality of first redistribution layers and a plurality of second redistribution layers that are vertically and alternately stacked in a vertical direction that is perpendicular to a bottom surface of the redistribution substrate;
• a logic chip on the redistribution substrate;
• a chip stack on the redistribution substrate, the chip stack including a plurality of memory chips that are vertically stacked;
• a plurality of first connection terminals connecting the redistribution substrate to the logic chip and the chip stack;
• and
• a plurality of second connection terminals connecting the package substrate to the redistribution substrate,
• wherein each of the first redistribution layers includes
• a first dielectric layer, and
• a first redistribution pattern that includes a first via part and a first pad part connected to the first via part, the first via part penetrating the first dielectric layer, and the first pad part being on a top surface of the first dielectric layer,
• wherein each of the second redistribution layers includes
• a second dielectric layer on an underlying first dielectric layer of an underlying first redistribution layer, and
• a second redistribution pattern that includes a second via part and a second pad part connected to the second via part, the second via part penetrating a portion of the second dielectric layer, and the second pad part is in the second dielectric layer,
• wherein the first redistribution pattern includes
• a first metal pattern on the first dielectric layer, and
• a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern,
• wherein the second redistribution pattern includes
• a second metal pattern in the second dielectric layer, and
• a second barrier pattern that is between the second dielectric layer and a bottom surface of the second metal pattern, and between the second dielectric layer and a sidewall of the second metal pattern, and
• wherein the second dielectric layer is on the first dielectric layer and directly contacts a sidewall of the first metal pattern.

A semiconductor package, comprising:

• a package substrate;
• a redistribution substrate on the package substrate, the redistribution substrate including first and second redistribution patterns that have respective bottom surfaces that are at different distances from a bottom surface of the redistribution substrate in a vertical direction that is perpendicular to the bottom surface of the redistribution substrate;
• a logic chip on the redistribution substrate;
• a plurality of chip stacks on the redistribution substrate, each of the plurality of chip stacks including a plurality of memory chips that are vertically stacked;
• a plurality of first connection terminals connecting the redistribution substrate to the logic chip and the plurality of chip stacks;
• a plurality of second connection terminals connecting the package substrate to the redistribution substrate;
• a molding layer on the redistribution substrate and covering the logic chip and the plurality of chip stacks, the molding layer having a sidewall aligned with a sidewall of the redistribution substrate;
• and
• a heat radiation structure disposed on the package substrate,
• wherein the first redistribution pattern includes
• a first metal pattern on a first dielectric layer, and
• a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern,
• wherein the second redistribution pattern includes
• a second metal pattern in a second dielectric layer, and
• a second barrier pattern that is between the second dielectric layer and a bottom surface of the second metal pattern, and between the second dielectric layer and a sidewall of the second metal pattern, and
• wherein the second dielectric layer is on the first dielectric layer and directly contacts a sidewall of the first metal pattern.