Simultaneous lower tail verify with upper tail verify

A method for operating non-volatile storage, the method comprising:

• applying a program voltage to a word line connected to a first set of memory cells on first NAND strings and a second set of memory cells on second NAND strings, the first set of memory cells targeted for programming to a first data state and the second set of memory cells targeted for programming to a second data state;
• applying a reference voltage to the word line after applying the program voltage;
• applying a first voltage to a first set of bit lines connected to the first NAND strings while applying the reference voltage to the word line;
• applying a second voltage to a second set of bit lines connected to the second NAND strings while applying the reference voltage to the word line, the second voltage having a different magnitude than the first voltage to result in a first effective reference level for the first set of memory cells and a second effective reference level for the second set of memory cells;
• sensing the first set of memory cells and the second set of memory cells in response to applying the reference voltage;
• and
• determining at least one fail bit count based on sensing the first set of memory cells and the second set of memory cells, the at least one fail bit count includes over-programmed memory cells in the first set and memory cells in the second set that have not yet been programmed to the second data state.

A non-volatile storage system, the system comprising:

• a three-dimensional memory structure having NAND strings, word lines, and bit lines, wherein the word lines are connected to memory cells on the NAND strings, wherein the bit lines are connected to the NAND strings;
• and
• one or more control circuits configured to connect to the three-dimensional memory structure, the one or more control circuits configured to:
• apply a first program voltage to a selected word line connected to a selected group of memory cells on a set of the NAND strings, the selected group of memory cells including a first set of memory cells targeted for programming to a first data state and a second set of memory cells targeted for programming to a second data state, wherein the first data state has a first target threshold voltage distribution that is lower than a second target threshold voltage distribution of the second data state;
• verify whether memory cells in the first set of memory cells are programmed to the first data state in response to the first program voltage;
• store an indication that a first memory cell in the first set has been programmed to the first data state in response to the first memory cell passing program verify after applying the first program voltage;
• apply a second program voltage to the selected word line after verifying whether memory cells in the first set of memory cells are programmed to the first data state;
• inhibiting the first memory cell from programming while applying the second program voltage to the selected word line in response to the indication that the first memory has been programmed to the first data state;
• over-ride the indication that the first memory cell has been programmed to the first data state to enable determining whether the first memory cell is over-programmed while simultaneously verifying whether memory cells in the second set of memory cells are programmed to the second data state;
• and
• simultaneously verify whether memory cells in the second set of memory cells are programmed to the second data state in response to the second program voltage while determining whether memory cells in the first set are over-programmed.