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US 12,367,938 B2Granted
Semiconductor memory with different threshold voltages of memory cells
AssigneeKioxia Corporation
InventorsNoboru Shibata, Hironori Uchikawa
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.
Claims16
A semiconductor memory comprising:
- first to N-th memory cells, N being an integer of 3 or more;
- first to N-th bit lines connected to the first to N-th memory cells, respectively;
- first to N-th latch circuits connected to the N-th bit lines;
- and
- a controller, wherein
- each of threshold voltages of the first to N-th memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, a third threshold voltage higher than the second threshold voltage, and a fourth threshold voltage higher than the third threshold voltage,
- data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell, based on a data allocation,
- the controller is configured to perform a read operation for one bit data based on the first to N-th memory cells, respectively,
- the controller applies, to read the data of one of the first bit, the second bit, the third bit, the fourth bit, the fifth bit, or the sixth bit, one or more kinds of read voltages to gates of the first to N-th memory cells in the read operation to cause the first to N-th latch circuits to store first to N-th interim data, respectively, and output the read data depending on the data allocation, and
- in the data allocation, a combination of the first to N-th memory cell commonly each set with the fourth threshold voltage does not overlap with another combination.
7 more elements
A semiconductor memory comprising:
- a first memory cell;
- a first bit line connected to the first memory cell;
- a first latch circuit connected to the first bit line;
- a second memory cell;
- a second bit line connected to the second memory cell;
- a second latch circuit connected to the second bit line;
- and
- a controller, wherein
- a threshold voltage of each of the first and second memory cells is set to any of at least three threshold voltage levels including a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage,
- data of at least three bits including a first bit, a second bit and a third bit is stored using a combination of the threshold voltages of the first and second memory cells based on a data allocation,
- the controller is configured to perform a read operation on the first and second memory cells for at least one bit data,
- the controller, to read the data of one of the first bit, the second bit, or the third bit, applies at least one kind of read voltage to gate of the first and second memory cells in the read operation to cause the first and second latch circuits to store first and second interim data, respectively, and output the read data depending on the data allocation, and
- in the data allocation, a combination of the first and second memory cells each set with the third threshold voltage does not overlap with another combination.
10 more elements
A semiconductor memory comprising:
- a first memory cell;
- a first bit line connected to the first memory cell;
- a first latch circuit connected to the first bit line;
- a second memory cell;
- a second bit line connected to the second memory cell;
- a second latch circuit connected to the second bit line;
- and
- a controller, wherein
- a threshold voltage of each of the first and second memory cells is set to any of at least eight threshold voltage levels including a first threshold voltage, a second threshold voltage higher than the first threshold voltage, a third threshold voltage higher than the second threshold voltage, a fourth threshold voltage higher than the third threshold voltage, a fifth threshold voltage higher than the fourth threshold voltage, a sixth threshold voltage higher than the fifth threshold voltage, a seventh threshold voltage higher than the sixth threshold voltage, and an eighth threshold voltage higher than the seventh threshold voltage,
- data of at least six bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit and a sixth bit is stored using a combination of the threshold voltages of the first and second memory cells, based on a data allocation,
- the controller is configured to perform a read operation on the first and second memory cells for at least one bit data, and
- the controller applies, to read the data of one of the first bit, the second bit, the third bit, the fourth bit, or the fifth bit, at least one kind of read voltage to gates of the first and second memory cells in the read operation to cause the first to N-th latch circuits to store first to N-th interim data, respectively, and output the read data depending on the data allocation, and
- in the data allocation, a combination of the first and second memory cells each set with the third threshold voltage does not overlap with another combination.
10 more elements
Dependencies are inferred from the claim text.