Non-homogeneous chiplets
AssigneeAdvanced Micro Devices, Inc.
InventorMatthaeus G. Chajdas
Life of this patent
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Abstract
A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.
Claims20
A parallel processing unit comprising:
- a first semiconductor die with a common set of circuitry modules and a first set of supporting circuitry modules, wherein the common set of circuitry modules includes at least one shader engine;
- a second semiconductor die with the common set of circuitry modules and a second set of supporting circuitry modules that is different than the first set of supporting circuitry modules, wherein the second set of supporting circuitry modules includes one or more additional shader engines;
- and
- an interconnect connecting the first semiconductor die and the second semiconductor die.
A method, comprising:
- receiving an indication of multiple commands for processing at a parallel processing unit;
- routing a first command of the multiple commands to a first semiconductor die disposed on the parallel processing unit, the first semiconductor die comprising a common set of circuitry modules and a first set of supporting circuitry modules, the common set of circuitry modules comprising at least one shader engine;
- and
- routing a second command of the multiple commands to a second semiconductor die disposed on the parallel processing unit, the second semiconductor die comprising the common set of circuitry modules and a second set of supporting circuitry modules that is different than the first set of supporting circuitry modules, the second set of supporting circuitry modules comprising one or more additional shader engines.
A device, comprising:
- a first semiconductor die comprising a first set of supporting circuitry modules, wherein the first set of supporting circuitry modules includes at least one shader engine;
- a second semiconductor die comprising a second set of supporting circuitry modules that is different than the first set of supporting circuitry modules, wherein the second set of supporting circuitry modules includes one or more additional shader engines;
- and
- an interconnect connecting the first semiconductor die and the second semiconductor die;
- wherein the first semiconductor die and the second semiconductor die are addressable as a single parallel processing unit.
Dependencies are inferred from the claim text.