Low latency memory access
AssigneeRambus Inc.
InventorFrederick A. Ware
Life of this patent
Estimating the term…
Abstract
A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.
Claims18
A memory component, comprising:
- a memory core;
- synchronous control circuitry to, based on the memory component being in a first mode, access the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal received via a first synchronous timing reference interface;
- and
- asynchronous control circuitry to, based on the memory component being in a second mode, access the memory core in response to second command, second control, and second address information received via an asynchronous sampling of signals at the first set of links and a second set of links using a second timing signal received via an asynchronous timing reference interface, the second set of links to communicate data bidirectionally when the memory component is in the first mode.
A method of operation within a memory component having a memory core, the method comprising:
- based on the memory component being in a first mode, accessing the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal received via a first synchronous timing reference interface;
- and
- based on the memory component being in a second mode, accessing the memory core in response to second command, second control, and second address information received via an asynchronous sampling of signals at the first set of links and at a second set of links using a second timing signal received via an asynchronous timing reference interface, the second set of links communicating data bidirectionally when the memory component is in the first mode.
A memory component, comprising:
- a memory core;
- means for, based on the memory component being in a first mode, accessing the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal received via a first synchronous timing reference interface;
- and
- means for, based on the memory component being in a second mode, accessing the memory core in response to second command, second control, and second address information received via an asynchronous sampling of signals at the first set of links and a second set of links using a second timing signal received via an asynchronous timing reference interface, the second set of links to communicate data bidirectionally when the memory component is in the first mode.
Dependencies are inferred from the claim text.