Electronic device with reduced process spread bandgap

An electronic device comprising:

• a terminal configured for receiving a bandgap voltage reference (VBG) generated by incorporating a first base-emitter voltage (VBE1), wherein the VBE1 Is subject to process variation;
• a first transistor comprising a base configured to be exposed to the VBG, wherein the first transistor is biased with a constant collector current (IC) corresponding with the VBE1, and is configured for providing a shifted voltage (VE) based on decreasing the VBG by a second base-emitter voltage (VBE2), and wherein the VBE2 is subject to the process variation;
• a second transistor of the same type as the first transistor, comprising an emitter configured to be exposed to the VE, wherein the second transistor is biased with a constant base current (IB) and is configured for providing a restored bandgap voltage (VBG2) based on increasing the VE by a third base-emitter voltage (VBE3);
• a branch connected to the emitter of the first transistor and to the emitter of the second transistor, so that the branch is configured to carry a summed emitter current (IE);
• a first current mirror arranged to mirror the IE, wherein the first current mirror comprises:
• a first branch configured for carrying a scaled base current (β*IB) and a core current (ICORE);
• a second branch configured for carrying the IE
• the first branch of the first current mirror comprising
• a second current mirror arranged to mirror the β*IB supplied to the collector of the second transistor;
• a third transistor comprising a base configured to be exposed to the IB, wherein the third transistor is configured for providing the β*IB in the first branch to be summed with the ICORE;
• and
• a terminal arranged to supply the ICORE, into the first branch to be summed with the β*IB.

An electronic device comprising:

• a terminal configured for receiving a bandgap voltage reference (VBG) generated by incorporating a first base-emitter voltage (VBE1), wherein the VBE1 is subject to process variation;
• a first transistor comprising a base configured to be exposed to the VBG, wherein the first transistor is biased with a constant collector current (IC) corresponding with the VBE1, and is configured for providing a shifted voltage (VE) based on decreasing the VBG by a second base-emitter voltage (VBE2), and wherein the VBE2 is subject to the process variation;
• a second transistor of the same type as the first transistor, comprising an emitter configured to be exposed to the VE, wherein the second transistor is biased with a constant base current (IB) and is configured for providing a restored bandgap voltage (VBG2) based on increasing the VE by a third base-emitter voltage (VBE3);
• a branch connected to the emitter of the first transistor and to the emitter of the second transistor, so that the branch is configured to carry a summed emitter current (IE);
• a first current mirror arranged to mirror the IE, wherein the first current mirror comprises:
• a first branch configured for carrying a scaled base current (β*IB), and a core current (ICORE);
• a second branch configured for carrying the IE:
• the first branch of the first current mirror comprising
• a second current mirror arranged to mirror the ICORE supplied to the collector of the first transistor;
• and
• a third transistor arranged in parallel to the second current mirror of the first branch, wherein the third transistor comprises a base configured to be exposed to the IB, and wherein the third transistor is configured for providing the β*IB into the first branch to be summed with the ICORE.