Fault detection circuit
AssigneeTexas Instruments Incorporated
InventorWeibing Jing
Life of this patent
Estimating the term…
Abstract
Fault detection circuits and methods. An example of a fault detection circuit includes a comparator configured to compare a voltage at a voltage terminal with a reference voltage, a digital logic circuit coupled to a test terminal and configured to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the digital logic circuit including at least one digital logic gate, and an edge detection circuit configured to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the test terminal.
Claims26
A circuit comprising:
- a first logic gate having a first input coupled to a first terminal;
- a second logic gate having a first input coupled to a second terminal, an output of the second logic gate coupled to a second input of the first logic gate;
- a first logic circuit;
- a voltage comparator having first and second comparator inputs and a comparator output, the first comparator input coupled to a voltage terminal, the second comparator input coupled to a reference voltage terminal, and the comparator output coupled to an input of the first logic circuit;
- a delay device having an input coupled to the second terminal, and an output of the delay device is coupled to a second input of the second logic gate;
- and
- a second logic circuit having a first input coupled to an output of the first logic gate, a second input coupled to an output of the first logic circuit, and having at least one fault detection output.
A circuit comprising:
- a voltage comparator having first and second comparator inputs and a comparator output, the first comparator input coupled to a reference voltage terminal;
- a first logic circuitry coupled to a first terminal, a second terminal, and the comparator output;
- and
- a delay device coupled between the second terminal and the first logic circuitry, the delay device configurable to produce a delayed copy of a test signal applied at the second terminal;
- wherein the first logic circuitry is configurable to produce a monitor signal based on a combination of the test signal, the delayed copy of the test signal, and a test voltage at the first terminal, and to produce a fault signal indicative of the fault based on a failure of the monitor signal to transgress a threshold value within a time period.
A circuit comprising:
- a comparator configurable to compare a voltage at a voltage terminal with a reference voltage;
- a first logic circuit coupled to a first terminal and configurable to receive, responsive to the voltage at the voltage terminal being less than the reference voltage as indicated by the comparator, a test signal, the first logic circuit including at least one digital logic gate;
- and
- an edge detection circuit configurable to (a) monitor a signal produced at an output of the at least one digital logic gate, and (b) based on the signal failing to transgress a threshold within a time period, providing a fault signal indicating detection of a fault at the first terminal.
Dependencies are inferred from the claim text.