Spin hall device, method for obtaining hall voltage, and max pooling method

A system for max pooling of multiple input data, comprising:

• a spin Hall device, a microprocessor, and a random access memory, a digital-to-analog converter and an analog-to-digital converter respectively connected to the microprocessor, wherein the random access memory, the digital-to-analog converter, the spin Hall device, the analog-to-digital converter, and the microprocessor are connected in sequence;
• the microprocessor is configured to control the digital-to-analog converter and the analog-to-digital converter;
• the digital-to-analog converter is configured to convert the input data into an analog current;
• the spin Hall device is configured to receive the analog current, and obtain a Hall voltage corresponding to a max current in the analog current;
• the analog-to-digital converter is configured to convert the Hall voltage corresponding to the max current into a digital quantity;
• the microprocessor is further configured to receive the digital quantity;
• and
• the spin Hall device comprising a cobalt ferroboron layer, wherein a top view and a bottom view of the spin Hall device are completely the same as a cross-shaped graph that has two axes of symmetry perpendicular to each other and equally divided by each other.

An analog computation neural network acceleration system, comprising a 1T1R crossbar array, a spin Hall device, an analog-to-digital converter, and a microprocessor, wherein comprising a cobalt ferroboron layer, wherein a top view and a bottom view of the spin Hall device are completely the same as a cross-shaped graph that has two axes of symmetry perpendicular to each other and equally divided by each other;

• the 1T1R crossbar array is configured to multiply and accumulate convolution computations by Kirchhoff's law under the control of the microprocessor to obtain multiply-accumulate data;
• the spin Hall device is configured to process the multiply-accumulate data to obtain a Hall voltage;
• the analog-to-digital converter is configured to convert the Hall voltage into a digital signal under the control of the microprocessor;
• and
• the microprocessor is configured to receive the digital signal;
• the analog computation neural network acceleration system further comprising:
• a power amplifier, an operational amplifier, a filter, and a low dropout linear regulator, wherein the 1T1R crossbar array, the power amplifier, the spin Hall device, the operational amplifier, the filter, the analog-to-digital converter, and the microprocessor are connected in sequence;
• the power amplifier is configured to amplify an electrical signal of the multiply-accumulate data to obtain an amplified electrical signal;
• the spin Hall device is configured to process the amplified electrical signal to obtain a Hall voltage;
• the operational amplifier is configured to amplify the Hall voltage to obtain an amplified Hall voltage;
• the filter is configured to filter the amplified Hall voltage to obtain a filtered Hall voltage;
• and
• the analog-to-digital converter is configured to convert the filtered Hall voltage into a digital signal under the control of the microprocessor.