US 12,364,006 B2Granted

Integrated circuit and method of forming same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChih-Yu Lai, Chih-Liang Chen

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Abstract

An integrated circuit includes a set of transistors including a set of active regions, a set of power rails, a first set of conductors and a first conductor. The set of active regions extends in a first direction, and is on a first level. The set of power rails extends in the first direction and is on a second level. The set of power rails has a first width. The first set of conductors extends in the first direction, is on the second level, and overlaps the set of active regions. The first set of conductors has a second width. The first conductor extends in the first direction, is on the second level and is between the first set of conductors. The first conductor has the first width, electrically couples a first transistor of the set of transistors to a second transistor of the set of transistors.

Claims20

Dependent claims

An integrated circuit comprising:

a set of transistors including a set of active regions, the set of active regions extending in a first direction, and being on a first level of a substrate, wherein the set of active regions comprises:
a first active region extending in the first direction, the first active region corresponding to a first drain/source of a first transistor of the set of transistors;
a set of power rails extending in the first direction, configured to supply a first supply voltage or a second supply voltage to the set of transistors, and being on a second level different from the first level, the set of power rails having a first width;
a first set of conductors extending in the first direction, being on the second level, being separated from the set of power rails in a second direction different from the first direction, and overlapping the set of active regions, the first set of conductors having a second width different from the first width;
a first conductor extending in the first direction, being on the second level and being between the first set of conductors, the first conductor having the first width, and the first conductor electrically coupling the first transistor of the set of transistors to a second transistor of the set of transistors;
and
a first contact of the first drain/source, the first contact extending in the second direction, being on a third level different from the first level and the second level, and overlapping the first active region.

4 more elements

An integrated circuit comprising:

a first active region extending in a first direction, and being on a first level of a substrate;
a second active region extending in the first direction, being on the first level of the substrate, and being separated from the first active region in a second direction different from the first direction;
a set of power rails extending in the first direction, configured to supply a first supply voltage or a second supply voltage, and being on a second level different from the first level;
a first conductor extending in the first direction, overlapping the first active region, being between the set of power rails, and having a first width;
a second conductor extending in the first direction, overlapping the second active region, being between the set of power rails, and having the first width;
a third conductor extending in the first direction, being on the second level and being between the first conductor and the second conductor, the third conductor having a second width different from the first width, and the third conductor electrically coupling a first region of the first active region to a first region of the second active region;
and
a first set of conductors extending in the second direction, being on a third level different from the first level and the second level, the first set of conductors overlapping the third conductor.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/444,923Filed 12 Aug 2021
Published: US 2023/0050555 A116 Feb 2023
Granted: 15 Jul 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 84/907
Comprising field effect technology: cMOS gate arrays
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts