A method for fabricated a stacked multilayer 3D GaN high electron mobility transistor (HEMT) structure, said method comprising:
- providing a substrate;
- forming a first layer GaN HEMT, which includes:
- forming a first multilayer epitaxial structure on said substrate, said first multilayer epitaxial structure been formed by sequentially growing a first n-type GaN layer, a first n-type AlGaN layer, and a first doped GaN layer on said substrate, wherein said first doped GaN layer is a p-type GaN layer or an n-type GaN layer;
- defining a first layer device area by utilizing a photomask on said first multilayer epitaxial structure, and removing said first n-type GaN layer, said first n-type AlGaN layer and said first doped GaN layer outside said first layer device area by an etching process;
- defining a first layer gate region on said first doped GaN layer by a photomask, and said first doped GaN layer outside said first layer gate region been removed to expose said first n-type AlGaN layer by an etching process to form said first layer gate region;
- forming a first drain metal region and a first source metal region on said first n-type AlGaN layer outside said first layer gate region;
- forming a first gate metal on said first layer gate region;
- forming a first protection layer on said first n-type AlGaN layer, said first drain metal, said first source metal and said first gate metal;
- forming a plurality of first layer through holes in said first protective layer by a photomask and etching process for respectively connecting said first drain metal, said first source metal and said first gate metal to outside of said first protective layer;
- forming a first dielectric layer to cover said first layer GaN HEMT;
- forming a second layer GaN HEMT, which includes:
- forming a second multilayer epitaxial structure on said first dielectric layer, said second multilayer epitaxial structure been formed by sequentially growing a second n-type GaN layer, a second n-type AlGaN layer, and a second doped GaN layer on said first dielectric layer, wherein said second doped GaN layer is a p-type GaN layer or an n-type GaN layer;
- defining a second layer device area by utilizing a photomask on said first multilayer epitaxial structure, and removing said second n-type GaN layer, said second n-type AlGaN layer and said second doped GaN layer outside said second layer device area by an etching process;
- defining a second layer gate region on said second doped GaN layer by a photomask, and said second doped GaN layer outside said second layer gate region been removed to expose said first n-type AlGaN layer by an etching process to form said second layer gate region;
- forming a second drain metal region and a second source metal region on said second n-type AlGaN layer outside said second layer gate region;
- forming a second gate metal on said second layer gate region;
- forming a second protection layer on said second n-type AlGaN layer, said second drain metal, said second source metal and said second gate metal;
- forming a plurality of second layer through holes in said second protective layer by a photomask and an etching process for respectively connecting said second drain metal, said second source metal and said second gate metal to outside of said second protective layer;
- forming a source metal interconnection structure, a drain metal interconnection structure and a gate metal interconnection structure to respectively connect between said first source electrode, said first drain electrode and said first gate electrode of said first layer GaN HEMT structure and said second source electrode, said second drain electrode and said second gate electrode of said second layer GaN HEMT structure;
- forming a second dielectric layer to cover said second layer GaN HEMT.