# US 12,363,895 B2 · Integrated assemblies and methods of forming integrated assemblies

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- Number: US 12,363,895 B2
- Document ID: US12363895B2
- Status: Granted
- Kind: B2
- Application number: 18/676,056
- Filed: 2024-05-28
- Published: 2024-09-19
- Granted: 2025-07-15
- Earliest claimed: 2015-11-23
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Justin B. Dorhout; Kunal R. Parekh; Martin C. Roberts; Mohd Kamran Akhtar; Chet E. Carter; David Daycock
- Web page: https://patentgrep.com/patent/US12363895B2

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 20/383: {Channel doping programmed}
- H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 41/23: with source and drain on different levels, e.g. with sloping channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10P 32/30: Diffusion for doping of conductive or resistive layers
- H10P 32/302: {Doping polycrystalline silicon or amorphous silicon layers}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10P 72/0418: {for etching}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

## Claims

### Claim 1

An integrated assembly, comprising:
a semiconductor substate having an upper surface;
a stack comprising multiple materials over the upper surface;
a first opening within the stack;
a second opening within the stack and spaced from the first opening by an intervening region; in a cross-sectional view, each of the first opening and the second opening having a first sidewall opposing a second sidewall and an opening base;
a dielectric material within the first opening and the second opening and entirely covering each of the first sidewall and the second sidewall;
a first channel structure within the first opening and a second channel structure within the second opening, each channel structure having a first portion along the first sidewall and a second portion along the second sidewall and a joining region, the second portion being spaced from the first portion along a majority of a height of the sidewalls, and being connected to the first portion through the joining region along the opening base;
a gating structure extending within the intervening region, the gating structure having a first gating region extending along the second portion of the first channel structure, a second gating region extending along the first portion of second channel structure, and an interconnecting region extending laterally between the first and second gating regions;
a first insulative region over the interconnecting region and disposed between the first gating region and the second gating region, the first insulative region comprising silicon oxide;
a second insulative region below the interconnecting region and disposed between the first gating region and the second gating region, the second insulative region comprising silicon oxide and a high-k dielectric material; and
a metal oxide material over the gating structure.

### Claim 2 (depends on 1)

The integrated assembly of claim 1, further comprising first and second conductive structures extending through the metal oxide material, the first conductive structure being over the first channel structure and the second conductive structure being over the second channel structure.

### Claim 3 (depends on 1)

The integrated assembly of claim 1 wherein the metal oxide material comprises one or more members of the group consisting of hafnium oxide, zirconium oxide and aluminum oxide.

### Claim 4 (depends on 1)

The integrated assembly of claim 1 wherein a first part of the gating structure and the first channel structure are incorporated into a select device electrically coupled in series with a plurality of memory cells.

### Claim 5 (depends on 4)

The integrated assembly of claim 4 wherein memory cells comprised by the plurality of memory cells are vertically-stacked over the select device.

### Claim 6 (depends on 1)

The integrated assembly of claim 1 wherein the intervening region comprises an insulative stack having an upper region of a first insulative material, a lower region of the first insulative material and a middle region between the upper region and the lower region, the middle region comprising a second insulative material, and wherein the gating structure extends within the insulative stack.

### Claim 7

A select device construction comprising:
a first select device having a first channel region comprising a semiconductor channel material;
a second select device having a second channel region comprising the semiconductor channel material; and
a gating structure extending between the first and second select devices and being shared by the first and second select devices, the gating structure having a first gating region having a length along the first channel region, having a second gating region having the length along the second channel region, and having an interconnecting region extending between the first and second gating regions, the interconnecting region being narrower than the a length of the first and second gating regions.

### Claim 8 (depends on 7)

The select device construction of claim 7 wherein the interconnecting region of the gating structure is approximately centered along the length of the gating regions.

### Claim 9 (depends on 7)

The select device construction of claim 7 wherein the gating structure comprises a metal material throughout the first gating region, the second gating region and the interconnecting region.

### Claim 10 (depends on 7)

The select device construction of claim 7 wherein the first channel region and the second channel region each comprise a lower portion having a first dopant concentration and an upper portion having a second dopant concentration that differs from the first dopant concentration.

### Claim 11 (depends on 10)

The select device construction of claim 10 wherein the first gating region is along both the upper portion and the lower portion of the first channel region, and wherein the second gating region is along both the upper portion and the lower portion of the second channel region.

### Claim 12 (depends on 10)

The select device construction of claim 10 wherein the second dopant concentration is higher than the first dopant concentration.

### Claim 13 (depends on 7)

The select device construction of claim 7 wherein the gating structure extends within a stack of alternating first and second insulating materials; a bottom surface of the first and second gating regions being along a lower tier of first insulative material; a bottom surface of the interconnecting region being along a higher tier of first insulative material; and an intermediate tier of second insulative material being between the lower and higher tiers of the first insulative material.

### Claim 14 (depends on 13)

The integrated assembly of claim 13 wherein the first insulative material comprises silicon dioxide, and the second insulative material comprises a high-k oxide.