Apparatus and method for processing transmit data in a transmit data path including parallel FEC encoding

A method comprising:

• converting an input data stream having an input bit width to a first output data stream having a first output bit width and to a second output data stream having a second output bit width, the input data stream and the first output data stream in a transmit data path;
• performing forward error correction (FEC) encoding, in parallel with the transmit data path, on multiple received symbols of the second output data stream having the second output bit width for generating parity bits;
• inserting the generated parity bits in the first output data stream;
• and
• signaling a latency predictor with a clock count value for selection of a latency value, the latency predictor comprising a look up table of latency values respectively associated with clock count values, the latency value for adjustment of timing used for timestamping data stream communications in the transmit data path.

An apparatus comprising:

• a data width converter in a transmit data path, the data width converter including an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width;
• a forward error correction (FEC) encoder in parallel with the transmit data path, the FEC encoder including an input to receive the second output data stream at the second output bit width, the FEC encoder including an output to produce parity bits for respective ones of multiple received symbols of the second output data stream;
• a parity insertion circuit to insert the produced parity bits at respective intervals of the first output data stream;
• a latency predictor, the latency predictor operably coupled to the data width converter, the latency predictor comprising a look up table of latency values respectively associated with clock count values, the latency predictor to select a latency value from the look up table of latency values at least partially responsive to a clock count value received from the data width converter;
• and
• a timestamp circuit, the timestamp circuit to timestamp data stream communications in the transmit data path, the timestamp circuit operably coupled to the latency predictor, the timestamp circuit to receive the latency value from the latency predictor and to adjust timing of the timestamp circuit for timestamping at least partially based on the latency value.