Gated tri-state inverter, and method of operating same

A method of operating a gated tri-state (G3S) inverter, the method comprising:

• receiving a gating signal, an enable signal and an input signal;
• and
• when the enable signal has a first logical state, then generating an impedance state at an output node of the G3S inverter to be a high impedance irrespective of the input signal or the gating signal;
• and
• when the enable signal has a second logical state:
• and also when each of the gating signal and the input signal has a first logical state, then generating a signal at the output node of the G3S inverter which has a logical high state;
• or
• and also when each of the gating signal and the input signal has a second logical state, then generating a signal at the output node of the G3S inverter which has a logical low state.

A gated tri-state (G3S) inverter comprises:

• a first transistor of a first dopant type (D1 transistors), a tri-state inverter and a first transistor of a second dopant type (D21 transistor) coupled in series between a first reference voltage and second reference voltage, the second dopant type being different than the first dopant type;
• gate terminals of the first D1 transistor and the first D2 transistor being configured to receive an input signal of the G3S inverter;
• and
• the tri-state inverter being configured to receive three control signals including a gating signal, an enable signal and an enable bar signal,
• the tri-state inverter having four control terminals configured to receive the three control signals,
• two of the four control terminals being configured to receive a same one of the three control signals and
• the enable signal being configured to control an impedance state of an output node of the G3S inverter to be a high impedance irrespective of the input signal or the gating signal.