Voltage controlled attenuator

A voltage controlled attenuator comprising:

• at least one input configured to receive an input signal;
• a control signal input configured to receive a control signal that adjusts a level of attenuation applied to the input signal;
• at least one output configured to present an attenuated output signal, the attenuated output signal attenuation controlled by the control signal;
• at least one signal path, having one or more resistors and one or more inductors, which connect the at least one input to the at least one output;
• a first FET device having a drain terminal connected to one of the at least one signal path and a gate terminal configured to receive the control signal input, wherein a portion of the input signal is distributed across the FET device to either a ground or another of the at least one signal path to attenuate the input signal to create the attenuated output signal;
• and
• one or more control signal resistors between the control signal input and the gate terminal of the FET device;
• and
• one or more additional FET devices connected, drain terminal to source terminal, to the FET device;
• and
• one or more resistors connected between the drain terminal and a source terminal of each of the first FET device and the one or more additional FET devices.

A method for attenuating a signal comprising:

• receiving an input signal at a first signal path and a second signal path;
• receiving a control signal at a control signal input, the control signal determining an amount of attenuation to be applied to the input signal;
• applying the control signal to a gate terminal of two or more FET devices such that the control signal adjusts the resistance of the two or more FET devices, such that the two or more FET devices are series connected, drain terminal to source terminal, between the first signal path and the second signal path;
• inhibiting high frequency components in the control signal from reaching a gate terminal of the two or more FET devices with a resistor between the control signal input and the gate terminal of the two or more FET devices;
• responsive to the control signal adjusting the resistance of the two or more FET devices, diverting a portion of the input signal from the first signal path to the second signal path through the two or more FET devices which attenuates the input signal to create an attenuated output signal;
• maintaining a constant DC voltage across the drain and source terminal of each of the two or more FET devices when the two or more FET devices are off by establishing and maintaining a resistance, with a resistor, across each of the drain terminals and source terminals of the two or more FET devices;
• and
• outputting the attenuated output signal.

An attenuator comprising:

• a first input configured to receive a first input signal;
• a second input configured to receive a second input signal, wherein the first input signal and the second input signal form a differential input signal;
• a control signal input configured to receive a control signal that adjusts a level of attenuation of the differential input signal;
• a first output configured to present a first output signal;
• a second output configured to present a second output signal, wherein the first output signal and the second output signal form a differential output signal which, responsive to the control signal, is an attenuated version of the differential input signal;
• a first signal path, having one or more resistors, between the first input and the first output;
• a second signal path, having one or more resistors, between the second input and the second output;
• a first FET device, having a drain terminal, a source terminal and a control terminal, connected to the first signal path such that the drain terminal of the first FET device connects to the first signal path and the control terminal connects to the control signal input;
• at least one additional FET device, each having a drain terminal, a source terminal and a control terminal, series connected with the first FET device such that the control terminal of the first FET device and a control terminal of the at least one additional FET device connect to the control signal input;
• and
• one or more resistors connected between the drain terminal and the source terminal of each of the first FET device and the at least one additional FET device.