Class AB monticelli output stage design with bias temperature instability tolerance

A circuit comprising:

• a p-channel transistor having a gate, a source, and a drain;
• an n-channel transistor having a drain coupled to the drain of the p-channel transistor at an output of the circuit, the n-channel transistor having a gate and a source;
• a first transistor having first and second terminals and a control terminal, the control terminal of the first transistor coupled to the gate of the p-channel transistor, the first terminal coupled to the source of the p-channel transistor;
• a second transistor having first and second terminals and a control terminal, the first terminal of the second transistor coupled to the second terminal of the first transistor;
• first current mirror circuitry coupled to the second terminal of the second transistor;
• second current mirror circuitry coupled to the first current mirror circuitry, the second current mirror circuitry having a terminal;
• an operational amplifier having a first input coupled to the second terminal of the first transistor and to the first terminal of the second transistor, having a second input coupled to the output of the circuit, and having an output coupled to the control terminal of the second transistor;
• a current source having a first terminal coupled to the terminal of the second current mirror circuitry and having a second terminal coupled to the source of the n-channel transistor;
• and
• a third transistor having a control terminal coupled to the terminal of the second current mirror circuitry and to the first terminal of the current source, the third transistor having a first terminal coupled to the gate of the p-channel transistor and having a second terminal coupled to the gate of the n-channel transistor.

A circuit comprising:

• a p-channel transistor having a gate, a source, and a drain;
• an n-channel transistor having a drain coupled to the drain of the p-channel transistor at an output of the circuit, the n-channel transistor having a gate and a source;
• a first transistor having first and second terminals and a gate, the gate of the first transistor coupled to a gate of the p-channel transistor, the first terminal coupled to the source of the p-channel transistor;
• first current mirror circuitry coupled to the second terminal of the first transistor;
• second current mirror circuitry coupled to the first current mirror circuitry, and having a terminal;
• a second transistor having first and second terminals and a control terminal, the control terminal of the second transistor coupled to the terminal of the second current mirror circuitry, the first terminal of the second transistor coupled to the gate of the p-channel transistor, the second terminal of the second transistor coupled to the gate of the n-channel transistor;
• a current source having a first terminal coupled to the terminal of the second current mirror circuitry and to the gate of the second transistor and having a second terminal coupled to the source of the n-channel transistor;
• and
• a third transistor having a gate coupled to a gate of the n-channel transistor and having first and second terminals, the first terminal of the third transistor coupled to control terminal of the second transistor, the second terminal of the third transistor coupled to the source of the n-channel transistor.