Control switch of driving circuit, array substrate and display panel

An array substrate, comprising a driving circuit, a source lead, and a scan line driven by the driving circuit, wherein a control switch of the driving circuit comprises a thin film transistor, wherein the thin film transistor comprises:

• a source electrode, comprising at least two source branches that are arranged in parallel, and a source trunk connecting the at least two source branches together, wherein each source branch directly connected to the at least one source lead is a first source branch, and wherein the first source branch is connected to an end of the source trunk;
• a drain electrode, disposed in a same layer as the source electrode, comprising at least one drain branch and a drain trunk connecting the at least one drain branch together, wherein the at least one drain branch and the at least two source branches are arranged in parallel and alternately to form channels, and wherein each drain branch disposed adjacent to each first source branch is a first drain branch;
• and
• a gate electrode, disposed corresponding to the source electrode and the drain electrode;
• wherein an extension line of each of the at least one source lead is located between the respective first drain branch and the source trunk and doesn't overlap the respective first drain branch, wherein the extension line of each of the at least one source lead has a width equal to a width of the respective source lead, and wherein the extension line of each of the at least one source lead is collinear and aligned with the respective source lead;
• wherein the driving circuit comprises a frame start signal line, a gate voltage control line, a clock signal line and a plurality of gate driving units, wherein input ends of the gate driving unit are respectively connected to the frame start signal line, the gate voltage control line, and the clock signal line, and an output end of the gate drive unit is connected to the scan line to drive the scan line;
• the gate voltage control line is connected to a thin film transistor in the gate driving unit through the source lead;
• wherein the gate driving unit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor;
• a source electrode of the first thin film transistor is directly connected to the gate voltage control line and directly connected to a source electrode of the second thin film transistor through two source leads, respectively, and a drain electrode of the first thin film transistor is directly connected to a source electrode of the third thin film transistor and directly connected to a gate electrode of the fourth thin film transistor, and a gate electrode of the first thin film transistor is directly connected to a gate electrode of the second thin film transistor;
• a drain electrode of the second thin film transistor is directly connected to a source electrode of the fourth thin film transistor, and a gate electrode of the second thin film transistor is directly connected to a gate electrode of the fourth thin film transistor;
• a drain electrode of the third thin film transistor is directly connected to the frame start signal line, and a drain electrode of the fourth thin film transistor is directly connected to the clock signal line.

A control switch of a driving circuit, the control switch comprising a thin film transistor, the driving circuit further comprising at least one source lead connected to the thin film transistor, wherein the thin film transistor comprises:

• a source electrode, comprising at least two source branches that are arranged in parallel, and a source trunk connecting the at least two source branches together, wherein each source branch directly connected to the at least one source lead is a first source branch, and wherein the first source branch is connected to an end of the source trunk;
• a drain electrode, disposed in a same layer as the source electrode, comprising at least one drain branch and a drain trunk connecting the at least one drain branch together, wherein the at least one drain branch and the at least two source branches are arranged in parallel and alternately to form channels, and wherein each drain branch disposed adjacent to each first source branch is a first drain branch;
• and
• a gate electrode, disposed corresponding to the source electrode and the drain electrode;
• wherein an extension line of each of the at least one source lead is located between the respective first drain branch and the source trunk and doesn't overlap the respective first drain branch, wherein the extension line of each of the at least one source lead has a width equal to a width of the respective source lead, and wherein the extension line of each of the at least one source lead is collinear and aligned with the respective source lead;
• wherein the thin film transistor is connected to one source lead, and there is only one first source branch;
• each source branch not directly connected to the source lead is a second source branch, and a number of the second source branches is at least one;
• wherein each first drain branch is disposed between the first source branch and the respective second source branch, and wherein an extension line of the source lead is located between the first drain branch and the source trunk and does not overlap the first drain branch;
• wherein each drain branch not disposed adjacent to the first source branch is a second drain branch, and wherein there is at least one second drain branch, wherein the first drain branch and one second drain branch are respectively connected to both ends of the drain trunk;
• wherein each second drain branch is arranged at between two adjacent second source branches;
• wherein a difference between a length of each second drain branch and a length of the first drain branch is equal to a width of the source lead;
• wherein a length direction of the first drain branch and each second drain branch is a direction of extension of the first drain branch and the second drain branch.