US 12,361,119 B2Granted

Consistent speculation of pointer authentication

AssigneeApple Inc.

InventorsJohn D Pape, Deepankar Duggal, Christopher M Tsay, Andrew H Lin, Corey C Stappenbeck

Life of this patent

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Abstract

In an embodiment, a processor includes hardware circuitry which may be used to authenticate instruction operands. The processor may execute instructions that perform operand authentication both speculatively and non-speculatively. During speculative execution of such instructions, the processor may execute authentication such that no differences in observable state of the processor, relative to authentication result, are detectable via a side channel. During speculative execution, a result of authentication may be deferred until speculative execution of the instruction, and additional instructions, may be completed. Upon resolution of a condition that indicates acceptance of the speculative execution, a speculative execution result may cause a processor exception and stalling of execution at the instruction to be performed.

Claims20

Dependent claims

A processor, comprising:

an authentication circuit configured to authenticate instruction operands;
and
an execution circuit configured to speculatively execute, responsive to an unresolved condition, an instruction stream comprising a plurality of instructions including an instruction comprising authentication of an instruction operand, wherein to speculatively execute the instruction stream the execution circuit is configured to:
perform, using the authorization circuit, the authentication of the instruction operand, as part of speculatively executing the instruction, to generate an authentication result;
continue speculative execution of the instruction stream to generate an observable state of the processor independent of the generated authentication result, wherein to continue speculative execution the execution circuit is configured to:
complete speculative execution of the instruction;
and
speculatively execute at least one additional instruction of the plurality of instructions subsequent to completing speculative execution of the instruction;
and
defer reporting the generated authentication result until resolution of the condition.

7 more elements

A method, comprising:

speculatively executing, by an execution circuit of a processor responsive to an unresolved condition, an instruction stream comprising a plurality of instructions including an instruction comprising authentication of an instruction operand, the speculatively executing comprising:
performing the authentication of the instruction operand as part of speculatively executing the instruction to generate an authentication result;
continuing speculative execution of the instruction stream to generate an observable state of the processor independent of the generated authentication result, wherein continuing speculative execution comprises:
completing speculative execution of the instruction;
and
speculatively executing at least one additional instruction of the plurality of instructions subsequent to completing speculative execution of the instruction;
and
deferring reporting the generated authentication result until resolution of the condition.

5 more elements

A system, comprising:

a memory configured to store a plurality of instructions;
and
a processor comprising:
an authentication circuit configured to authenticate instruction operands;
and
an execution circuit configured to:
speculatively execute, responsive to an unresolved condition, an instruction stream comprising a plurality of instructions including an instruction comprising authentication of an instruction operand, wherein to speculatively execute the instruction stream the execution circuit is configured to:
perform, using the authorization circuit, the authentication of the instruction operand as part of speculatively executing the instruction to generate an authentication result;
continue speculative execution of the instruction stream to generate an observable state of the processor independent of the generated authentication result, wherein to continue speculative execution the execution circuit is configured to:
complete speculative execution of the instruction;
and
speculatively execute one or more of the plurality of instructions subsequent to completing speculative execution of the instruction;
and
execute, responsive to resolution of the condition indicating that the instruction stream is to be executed, the instruction stream, wherein to execute the instruction stream the execution circuit is configured to:
responsive to the authentication result indicating an authentication failure:
suspend processor execution at the instruction;
and
generate a processor fault.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/510,540Filed 15 Nov 2023 · us provisional application
Priority: 18 Sep 2023
Published: US 2025/0094567 A120 Mar 2025
Granted: 15 Jul 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 21/54
During program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow: by adding security routines or objects to programs
G06F 9/3806
For branches, e.g. hedging, branch folding: using address prediction, e.g. return stack, branch history buffer
G06F 9/3842
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: speculative instruction execution
G06F 21/556
Detecting local intrusion or implementing counter-measures: involving covert channels, i.e. data leakage between processes