Error correction memory device with fast data access
AssigneeMicron Technology, Inc.
InventorsScott E. Schaefer, Aaron P. Boehm
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.
Claims20
An apparatus, comprising:
- an array of memory cells of a memory;
- an interface configured to receive a write command from a host device;
- an error-correcting code circuit coupled with the interface and the array of memory cells and configured to identify an error in data based at least in part on performing an error correction operation on the data;
- and
- a buffer configured to output error control information and the data to the array of memory cells via a first data path that bypasses the error-correcting code circuit based at least in part on a first mode of operation or a second data path that comprises the error-correcting code circuit based at least in part on a second mode of operation, wherein the first data path and the second data path propagate the data indicated by a write operation to the array of memory cells.
A method, comprising:
- receiving, at a memory device comprising a memory array, a write command from a host device;
- determining whether to propagate data and error control information via a first data path that bypasses an error-correcting code circuit based at least in part on a first mode of operation or a second data path that comprises the error-correcting code circuit based at least in part on a second mode of operation, wherein the first data path and the second data path propagate the data indicated by a write operation to the memory array;
- and
- writing the data and the error control information to the memory array via the first data path that bypasses an error-correcting control circuit or the second data path that comprises the error-correcting code circuit based at least in part on the determination.
An apparatus, comprising:
- an array of memory cells of a memory;
- an interface configured to receive a write command associated with a write operation from a host device;
- an error-correcting code circuit coupled with the interface and the array of memory cells;
- and
- a buffer configured to output data and error control information to the array of memory cells via a first data path that bypasses the error-correcting code circuit based at least in part on a first mode of operation or a second data path that comprises the error-correcting code circuit based at least in part on a second mode of operation, wherein the first data path and the second data path propagate the data indicated by the write operation to the array of memory cells, wherein the array of memory cells is configured to store the data indicated by the write operation and the error control information generated by the host device.
Dependencies are inferred from the claim text.