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US 12,360,843 B2Granted
Multicore shared cache operation engine
AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Timothy David Anderson, Joseph Zbiciak, David E. Smith, Matthew David Pierson
Life of this patent
Estimating the term…
Abstract
Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.
Claims17
A circuit comprising:
- a memory mapped register configured to receive a memory access command;
- a buffer coupled to the memory mapped register and configured to store the memory access command;
- a trigger control channel configured to receive a trigger event associated with the memory access command and in response to the trigger control channel receiving the trigger event:
- obtain the memory access command;
- and
- load the memory access command into a subtiler, wherein the subtiler is configured to translate the memory access command into an instruction associated with a physical memory location;
- and
- a queue configured to receive the instruction and output the instruction to a memory associated with the physical memory location.
5 more elements
A circuit comprising:
- a plurality of interfaces configured to receive a memory access command, wherein the plurality of interfaces includes a memory mapped register and a packet streaming interface;
- a buffer coupled to the plurality of interfaces and configured to store the memory access command;
- a trigger control channel configured to receive a trigger event associated with the memory access command, wherein a trigger control channel configuration indicates which of the plurality of interfaces is used to obtain the memory access command, and in response to the trigger control channel receiving the trigger event:
- obtain the memory access command;
- and
- load the memory access command into a subtiler, wherein the subtiler is coupled to the buffer and configured to translate the memory access command into an instruction associated with a physical memory location;
- and
- a queue coupled to the subtiler and configured to receive the instruction and output the instruction to a memory associated with the physical memory location.
5 more elements
Dependencies are inferred from the claim text.