US 12,356,644 B2 · Gate tunnel current-triggered semiconductor controlled rectifier

Abstract

Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

Claims20

Dependent claims

A structure comprising:

a semiconductor layer having a first surface and a second surface opposite the first surface;
an Nwell in the semiconductor layer;
a Pwell in the semiconductor layer positioned laterally immediately adjacent to the Nwell;
a P-type diffusion region in the Nwell at the second surface and physically separated from a junction between the Nwell and the Pwell;
an N-type diffusion region in the Pwell at the second surface and physically separated from the junction;
and
a gate on the second surface between the P-type diffusion region and the N-type diffusion region, wherein the gate is offset from the junction, above only one of the Nwell and the Pwell, and physically separated from the P-type diffusion region and from the N-type diffusion region, and wherein a portion of the one of the Nwell and the Pwell below the gate and extending laterally to the junction is devoid of any additional diffusion regions.

4 more elements

A structure comprising:

a semiconductor layer having a first surface and a second surface opposite the first surface;
an Nwell in the semiconductor layer;
a Pwell in the semiconductor layer positioned laterally immediately adjacent to the Nwell;
a P-type diffusion region in the Nwell at the second surface and physically separated from a junction between the Nwell and the Pwell;
an N-type diffusion region in the Pwell at the second surface and physically separated from the junction;
a first gate on the second surface immediately adjacent to the Nwell and physically separated from the P-type diffusion region and from the junction;
and
a second gate on the second surface immediately adjacent to the Pwell and physically separated from the N-type diffusion region and from the junction, wherein a portion of the Nwell below the first gate and extending laterally to the junction and a portion of the Pwell below the second gate and extending laterally to the junction are devoid of any additional diffusion regions.

5 more elements

Dependencies are inferred from the claim text.

Gate tunnel current-triggered semiconductor controlled rectifier

Life of this patent

Gate tunnel current-triggered semiconductor controlled rectifier

Life of this patent

Abstract

Claims20