Method and apparatus for passing clock signals between time domains

Timestamp synchronization circuitry for reducing jitter in transmission of a timestamp across a clock domain boundary, the timestamp synchronization circuitry comprising:

• N parallel buffers in an origin clock domain, the N parallel buffers being configured to store N timestamps generated in N successive clock cycles in the origin clock domain;
• a modulo-N counter configured to generate a selection signal to indicate in which of the N parallel buffers a current timestamp is stored;
• and
• timestamp selection circuitry in a destination clock domain across the clock domain boundary, the timestamp selection circuitry being configured to apply an offset to the modulo-N counter in the destination clock domain, that accounts for both uncertainty in the modulo-N counter and instability in the N timestamps, to derive a selection signal that selects a stable timestamp from among the outputs of the N parallel buffers and to output the selected stable timestamp.

Timestamp synchronization circuitry for reducing jitter in transmission of a timestamp across a clock domain boundary, the timestamp synchronization circuitry comprising:

• N parallel buffer means in an origin clock domain, the N parallel buffer means being configured to store N timestamps generated in N successive clock cycles in the origin clock domain;
• modulo-N counter means configured to generate a selection signal to indicate in which of the N parallel buffer means a current timestamp is stored;
• and
• timestamp selection means in a destination clock domain across the clock domain boundary, the timestamp selection means being configured to apply an offset to the modulo-N counter means in the destination clock domain, that accounts for both uncertainty in the modulo-N counter means and instability in the N timestamps, to derive a selection signal that selects a stable timestamp from among the outputs of the N parallel buffer means and to output the selected stable timestamp.