Phase locked loop filter circuitry

A phase locked loop circuit comprising:

• a phase and frequency detector circuit;
• a charge pump circuit operatively connected to the phase and frequency detector circuit;
• a loop filter circuit operatively connected to the charge pump circuit, the loop filter circuit having a first transistor and a second transistor operatively connected with each other, a precharge switch and a capacitor operatively connecting the first and second transistor with a third transistor, a node located between the third transistor and the capacitor, wherein the node corresponds to a pole in a common gate stage of a feedback path, wherein the common gate stage is configured to create the pole in the feedback path at the node which leads to creation of a zero in an output transfer function associated with the loop filter circuit, and wherein the feedback path is configured to convert a right half plane zero to a left half plane zero for improving a transient response of the loop filter circuit;
• a common mode capacitor configured to convert conjugate poles to real poles, wherein the conjugate poles are generated by the common gate stage;
• a voltage-controlled oscillator circuit configured to receive an input from the loop filter circuit;
• and
• a divider circuit configured to receive an output from the voltage-controlled oscillator circuit.

A phase locked loop method comprising:

• providing a phase and frequency detector circuit and a charge pump circuit operatively connected to the phase and frequency detector circuit;
• receiving an input from the charge pump circuit at a loop filter circuit operatively connected to the charge pump circuit, the loop filter circuit having a first transistor and a second transistor operatively connected with each other, a precharge switch and a capacitor operatively connecting the first and second transistor with a third transistor, and a node located between the third transistor and the capacitor, wherein the node corresponds to a pole in a common gate stage of a feedback path, wherein the common gate stage is configured to create the pole in the feedback path at the node which leads to creation of a zero in an output transfer function associated with the loop filter circuit, and wherein the feedback path is configured to convert a right half plane zero to a left half plane zero for improving a transient response of the loop filter circuit;
• a common mode capacitor configured to convert conjugate poles to real poles, wherein the conjugate poles are generated by the common gate stage;
• receiving an input from the loop filter circuit at a voltage-controlled oscillator circuit;
• and
• providing an output from the voltage-controlled oscillator circuit to a divider circuit.