Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip

A multi-chip package comprising:

• a first semiconductor integrated-circuit (IC) chip comprising a first silicon substrate, a plurality of first transistors at a top surface of the first silicon substrate and a first interconnection scheme over the first silicon substrate and coupling to the plurality of first transistors;
• a second semiconductor integrated-circuit (IC) chip over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip comprises a second silicon substrate, a plurality of second transistors at a bottom surface of the second silicon substrate and a second interconnection scheme under the second silicon substrate and coupling to the plurality of second transistors, wherein the second interconnection scheme comprises a first silicon-oxide-containing layer and a first bonding pad each at a bottom of the second semiconductor integrated-circuit (IC) chip, wherein the first bonding pad is in an opening in the first silicon-oxide-containing layer and couples to the first semiconductor integrated-circuit (IC) chip, wherein the first bonding pad comprises a first copper layer in the opening in the first silicon-oxide-containing layer and a first adhesion metal layer having a first portion at a sidewall of the first copper layer and a second portion at a top of the first copper layer, wherein the first copper layer has a bottom surface coplanar with a bottom surface of the first silicon-oxide-containing layer, wherein the second semiconductor integrated-circuit (IC) chip has a first edge over the first semiconductor integrated-circuit (IC) chip and a second edge opposite to the first edge and over the first semiconductor integrated-circuit (IC) chip;
• a sealing layer over the first semiconductor integrated-circuit (IC) chip and at a same horizontal level as the second semiconductor integrated-circuit (IC) chip;
• a first metal via over the first semiconductor integrated-circuit (IC) chip and vertically in the sealing layer;
• a second metal via over the first semiconductor integrated-circuit (IC) chip, vertically in the sealing layer and coupling to the first bonding pad of the second semiconductor integrated-circuit (IC) chip;
• a first metal pad vertically over and coupling to the first metal via;
• a polymer layer over the second semiconductor integrated-circuit (IC) chip and sealing layer, wherein an opening in the polymer layer is vertically over the first metal pad and first metal via;
• and
• a first metal bump on the first metal pad, vertically over the first metal via and at a top of the multi-chip package, wherein the first metal bump couples to the first metal via through the first metal pad.