Multilayer stacking wafer bonding structure and method of manufacturing the same

A method of manufacturing a multilayer stacking wafer bonding structure, comprising:

• providing a logic wafer, wherein said logic wafer comprises a first substrate and a logic circuit layer on said substrate;
• providing a memory wafer, wherein said memory wafer comprises a second substrate, multiple oxide layers in trenches of said second substrate and a memory layer on surfaces of said second substrate and said oxide layers;
• bonding said memory layer of said memory wafer with said logic circuit layer of said logic wafer;
• performing a backside grinding step to remove parts of said second substrate, so that said second substrate becomes a silicon layer and said oxide layers are exposed from said silicon layer, and surfaces of said oxide layers and said silicon layer are flush;
• repeating aforementioned steps of providing said memory wafers and backside grinding process to sequentially stack and bond multiple memory wafers on said logic wafer to constitute a first multilayer stacking structure, wherein said oxide layers in said memory wafers are aligned with each other in a direction vertical to said first substrate;
• performing a photolithography process to form multiple first through-oxide via (TOV) holes, wherein said first TOV holes extend through all of said memory layers and said oxide layers in said first multilayer stacking structure to said logic circuit layer of said logic wafer, and said first TOV holes do not extend through any of said silicon layers in said memory wafers;
• filling said first TOV holes with conductive materials to form first TOVs;
• and
• forming via middle through-silicon vias (TSVs) in said logic wafer after said memory wafers are bonded, and said first TOVs formed in later process are connected with corresponding said via middle TSVs.