Spacer film scheme form polarization improvement
AssigneeTaiwan Semiconductor Manfacturing Company, Ltd.
InventorsTzu-Yu Lin, Yao-Wen Chang
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
Claims20
An integrated chip, comprising:
- a lower electrode;
- a high-k material structure disposed over the lower electrode;
- an upper electrode disposed over a central region of the high-k material structure;
- and
- a stressed dielectric spacer arranged on a peripheral region of the high-k material structure, wherein the high-k material structure has an orthorhombic phase concentration that varies between the central region and the peripheral region.
A device, comprising:
- a bottom electrode;
- a ferroelectric layer disposed on the bottom electrode;
- a top electrode disposed on the ferroelectric layer;
- and
- a spacer layer disposed on the ferroelectric layer and adjacent to the top electrode, wherein the ferroelectric layer has a higher concentration of orthorhombic phase within an edge region than within a central region.
A method of forming an integrated chip (IC), comprising:
- forming a lower electrode layer;
- forming a ferroelectric layer over the lower electrode layer;
- forming an upper electrode over the ferroelectric layer;
- forming a spacer onto the ferroelectric layer and adjacent to the upper electrode;
- patterning the ferroelectric layer and the lower electrode layer outside of the upper electrode and the spacer to form a ferroelectric data storage structure and a lower electrode;
- and
- wherein the ferroelectric data storage structure has a higher concentration of orthorhombic phase within a peripheral region that is directly below the spacer than within a central region.
Dependencies are inferred from the claim text.