System and method enabling software-controlled processor customization for workload optimization
AssigneeUnisys Corporation
InventorsAndrew Ward Beale, David Strong
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Abstract
A system and method for virtual processor customization based upon the particular workload placed upon the virtual processor by one or more execution contexts within a given program or process. The customization serves to optimize the virtual processor architecture based upon a determination as to the size and/or type or virtual execution registers optimally suited for supporting a given execution context. This results in a time-variant processor architecture which not only provides optimized computational attributes, but also affords a high degree of inherent process security.
Claims19
A system for defining and accessing registers comprising:
- at least one virtual processor comprising information indicative of at least one compiler that is adapted to analyze at least a portion of an executable context defining at least one particular process to executed upon at least one virtual processor and responsively produce at least one instruction set indicative of a virtual execution register context customized to support the at least one executable process;
- at least one virtual execution context memory comprising stored information defining a particular virtual processor state, wherein the information defining the particular virtual processor state is stored as register context information and paired memory context information in a specific portion of a first addressable memory and based, at least in part, upon the at least one instruction set, wherein the at least one virtual execution context memory is defined by software in a configurable random-access memory storage system at run-time to have the precise capacity based on the register context information and the paired memory context information that define the processor state;
- and
- the at least one virtual processor comprising information stored in a specific portion of a second addressable memory, the stored information defining at least one base register pointer, wherein the at least one base register pointer comprises at least one memory address enabling the at least one virtual processor to access the specific portion of the first addressable memory storing the information defining the particular virtual processor state.
A method for defining and accessing registers comprising:
- using a compiler, analyzing at least a portion of an executable context defining at least one particular process to executed upon at least one virtual processor and responsively produce at least one instruction set indicative of a virtual execution register context optimized to support the at least one executable process, wherein the compiler is a software construct adapted to interpret a language source code and emits a code file comprised of machine code;
- storing, in a specific portion of a first addressable memory, information based, at least in part, upon the at least one instruction set, wherein the stored information includes register context information and paired memory context information and defines a particular virtual processor state, wherein the specific portion of the first addressable memory is defined by software in a configurable random-access memory storage system at run-time to have the precise capacity based on the register context information and the paired memory context information that define the processor state;
- and
- virtualizing at least one processor comprising information stored in a specific portion of a second addressable memory, the stored information defining at least one base register pointer, wherein the at least one base register pointer comprises at least one memory address enabling the at least one virtual processor to access the specific portion of the first addressable memory storing the information defining the particular virtual processor state.
Dependencies are inferred from the claim text.