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US 12,353,883 B2Granted
Executing memory requests out of order
AssigneeImagination Technologies Limited
InventorsMark Landers, Martin John Robinson
Life of this patent
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AssigneeImagination Technologies Limited
InventorsMark Landers, Martin John Robinson
Estimating the term…
An on-chip cache is described which receives memory requests and in the event of a cache miss, the cache generates memory requests to a lower level in the memory hierarchy (e.g. to a lower level cache or an external memory). Data returned to the on-chip cache in response to the generated memory requests may be received out-of-order. An instruction scheduler in the on-chip cache stores pending received memory requests and effects the re-ordering by selecting a sequence of pending memory requests for execution such that pending requests relating to an identical cache line are executed in age order and pending requests relating to different cache lines are executed in an order dependent upon when data relating to the different cache lines is returned. The memory requests which are received may be received from another, lower level on-chip cache or from registers.
An instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the instruction scheduler comprising:
A method of operating an instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the method comprising:
A non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture an instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the instruction scheduler comprising:
Dependencies are inferred from the claim text.