Compliance and debug testing of a die-to-die interconnect

A method comprising:

• performing a first reset of a first die of a test package and a second reset of a second die of the test package, the first die comprising a reference die that is a known good die and the second die comprising a device under test;
• after performing the first reset and the second reset, training a sideband of an interconnect that couples the first die and the second die, the interconnect comprising a mainband and the sideband;
• and
• monitoring, using the first die, a progression of at least one link training state machine of the second die as part of a testing of the second die.

A package comprising:

• a first die comprising a central processing unit (CPU) and a protocol stack comprising:
• a die-to-die adapter comprising a plurality of first registers, the die-to-die adapter to communicate with protocol layer circuitry via a flit-aware die-to-die interface (FDI) and physical layer circuitry via a raw die-to-die interface (RDI), wherein the die-to-die adapter is to communicate message information, the message information comprising first information of a first interconnect protocol;
• and
• the physical layer circuitry coupled to the die-to-die adapter via the RDI, the physical layer circuity comprising a plurality of second registers, wherein the physical layer circuitry is to receive and output the first information to a second die via an interconnect having a mainband and a sideband,
• wherein the physical layer circuitry is to perform a link initialization of the interconnect and the sideband is to enable access to information in at least one of the plurality of first registers or at least one of the plurality of second registers to monitor a progression of at least one link training state machine of the second die as part of a testing of the second die;
• and
• the second die coupled to the first die via the interconnect, wherein the first die comprises a known good die and the second die comprises a device under test.