Technologies for radio frequency optimized interconnects for a quantum processor

A quantum processor die comprising:

• a plurality of spin qubits;
• and
• a plurality of waveguides on a surface of the quantum processor die to deliver signals to and from the plurality of spin qubits,
• wherein individual waveguides of the plurality of waveguides comprise a center signal conductor and two ground conductors,
• wherein each signal conductor on the surface of the quantum processor die is a signal conductor of one of the plurality of waveguides.

A method for fabricating a plurality of quantum processor dies, the method comprising:

• applying a first dielectric layer to a carrier substrate wafer, wherein the carrier substrate wafer has a diameter over 250 millimeters, wherein the carrier substrate wafer comprises low-doped silicon;
• applying a silicon layer over the first dielectric layer;
• fabricating a plurality of spin qubit arrays in the silicon layer, wherein individual spin qubit arrays of the plurality of spin qubit arrays correspond to a quantum processor die of the plurality of quantum processor dies;
• applying a second dielectric layer over the silicon layer;
• patterning a plurality of waveguides on a surface of the second dielectric layer to deliver signals to and from the plurality of spin qubit arrays, wherein individual waveguides of the plurality of waveguides comprise a center signal conductor and two ground conductors;
• patterning a plurality of ground rings, wherein individual ground rings of the plurality of ground rings correspond to a quantum processor die of the plurality of quantum processor dies, and wherein individual ground rings of the plurality of ground rings surround waveguides of the plurality of waveguides corresponding to the corresponding quantum processor die of the plurality of quantum processor dies;
• and
• singulating the carrier substrate wafer into the plurality of quantum processor dies.