Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures

An integrated circuit (IC) structure, comprising:

• a plurality of complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) structures, wherein individual ones of the CMOS FET structures comprise a Group IV crystalline material;
• and
• a plurality of back-end transistor structures over the CMOS FET structures, with one or more levels of interconnect metallization therebetween, wherein individual ones of the back-end transistor structures comprise:
• a substrate material;
• a channel material over the substrate material, the channel material of a first composition comprising oxygen and one or more metals;
• a gate electrode coupled to a sidewall of the channel material;
• a gate dielectric material between the gate electrode and the sidewall of the channel material;
• and
• a contact buffer material between the channel material and a source contact metallization or a drain contact metallization that is between the channel material and the substrate material, wherein the contact buffer material is of a second composition comprising oxygen and one or more metals.

A method of fabricating a transistor structure, the method comprising:

• forming a bottom one of a source or drain contact metallization;
• forming a first layer of a contact buffer material over the bottom one of the source or drain contact metallization;
• forming, over the first layer of a contact buffer material, a channel material of a first composition comprising oxygen and one or more metals;
• forming a second layer of the contact buffer material over the channel material, wherein each of the first and second layers of the contact buffer material is of a second composition comprising oxygen and one or more metals;
• forming a top one of a source or drain contact metallization over the second layer of the contact buffer material;
• forming a gate dielectric adjacent to a sidewall of the channel material;
• and
• forming a gate electrode adjacent to a sidewall of the gate dielectric.