Gate-all-around integrated circuit structures having dual nanoribbon channel structures

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having an uppermost nanowire, each nanowire of the first vertical arrangement of nanowires having a channel region;
• a first dielectric cap over the first vertical arrangement of nanowires, wherein the first dielectric cap is vertically spaced apart from the uppermost nanowire of the first vertical arrangement of nanowires, and wherein the first dielectric cap extends laterally across an entirety of the channel region of the uppermost nanowire of the first vertical arrangement of nanowires;
• a first gate stack over the first vertical arrangement of nanowires and over the first dielectric cap, the first gate stack vertically surrounding the channel region of each nanowire of the first vertical arrangement of nanowires, and the first gate stack vertically surrounding the first dielectric cap;
• a second vertical arrangement of nanowires laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires having an uppermost nanowire, each nanowire of the second vertical arrangement of nanowires having a channel region;
• a second dielectric cap over the second vertical arrangement of nanowires, wherein the second dielectric cap is vertically spaced apart from the uppermost nanowire of the second vertical arrangement of nanowires, and wherein the second dielectric cap extends laterally across an entirety of the channel region of the uppermost nanowire of the second vertical arrangement of nanowires;
• and
• a second gate stack over the second vertical arrangement of nanowires and over the second dielectric cap, the second gate stack vertically surrounding the channel region of each nanowire of the second vertical arrangement of nanowires, and the second gate stack vertically surrounding the second dielectric cap, wherein the second gate stack and the first gate stack have a same conductivity type.