Memory devices having vertical transistors and methods for forming the same

A memory system, comprising:

• a memory device configured to store data, and comprising:
• a first semiconductor structure comprising a peripheral circuit;
• a second semiconductor structure comprising:
• an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor;
• and
• a plurality of bit lines coupled to the memory cells, and a major axis of each of the plurality of bit lines extending in a second direction perpendicular to the first direction,
• wherein:
• a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction;
• and
• two adjacent vertical transistors of the vertical transistors in the second direction are mirror-symmetric to one another, each of the two adjacent vertical transistors comprising a respective semiconductor body, and each semiconductor body corresponding to only one gate structure at one side of the semiconductor body and in direct contact with a trench isolation at two sides of the trench isolation, and in the second direction, the semiconductor bodies being separated by the trench isolation;
• and
• a bonding interface between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface;
• and
• a memory controller coupled to the memory device and configured to control the array of memory cells through the peripheral circuit and the bit lines.

A three-dimensional (3D) memory device, comprising:

• a first semiconductor structure comprising a peripheral circuit;
• and
• a second semiconductor structure comprising:
• an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor;
• and
• a plurality of bit lines coupled to the memory cells, and a major axis of each of the plurality of bit lines extending in a second direction perpendicular to the first direction,
• wherein:
• a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction;
• and
• two adjacent vertical transistors of the vertical transistors in the second direction are mirror-symmetric to one another, and each of the two adjacent vertical transistors comprises a respective semiconductor body separated from each other, in the second direction, by a trench isolation, a gate structure of one of the vertical transistors being arranged at only one side of a corresponding semiconductor body of the vertical transistor, and the corresponding semiconductor body being arranged between the gate structure and the trench isolation in the second direction.