Self-guided placement of memory device component packages

An integrated circuit device, comprising:

• a package having a quadrilateral shape;
• a grid array positioned on a first side of the package, the grid array including a plurality of connection points;
• a first self-correcting alignment pin on the first side of the package;
• and
• a second self-correcting alignment pin on the first side of the package,
• wherein the first self-correcting alignment pin and the second self-correcting alignment pin each have a conically shaped tapered portion;
• and
• wherein the first self-correcting alignment pin and the second self-correcting alignment pin are positioned opposite the grid array along a diagonal axis bisecting the package, and
• wherein the integrated circuit device is coupled to a substrate, the substrate comprising a connection pad configured to interface with the integrated circuit device;
• and
• wherein the first self-correcting alignment pin and the second self-correcting alignment pin interface with a first self-correcting alignment receptacle and a second self-correcting alignment receptacle, respectively, of the connection pad,
• wherein the first self-correcting alignment receptacle and the second self-correcting alignment receptacle have a tapered shape complementary to the conically shaped tapered portion of the first self-correcting alignment pin and the second self-correcting alignment pin, and
• wherein the first self-correcting alignment and the second self-correcting alignment receptacles do not penetrate completely through the substrate.

An electronic assembly, comprising:

• a printed circuit board including a connection pad;
• and
• an integrated circuit package having a grid array;
• wherein the integrated circuit package includes a first self-correcting alignment pin and a second self-correcting alignment pin that have a tapered portion, and
• wherein the connection pad is interfaced with the grid array, the connection pad including a first self-correcting alignment receptacle receiving the first self-correcting alignment pin and a second self-correcting alignment receptacle receiving the second self-correcting alignment pin, and
• wherein the first self-correcting alignment pin is received within the first self-correcting alignment receptacle and the second self-correcting alignment pin is received within the second self-correcting alignment receptacle such that the grid array integrated circuit package maintains an alignment with the connection pad,
• wherein the first self-correcting alignment receptacle includes a tapered shape complementary with the tapered portion of the first self-correcting alignment pin and the second self-correcting alignment receptacle includes a tapered shape complementary with the tapered portion of the second self-correcting alignment pin;
• and wherein the first self-correcting alignment receptacle and the second self-correcting alignment receptacle do not penetrate completely through a substrate of the printed circuit board.