Integrated circuit transceiver array synchronization

An apparatus comprising:

• a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs;
• a beamformer processor coupled to the plurality of transceiver IC subarrays, wherein the beamformer processor is configured to generate at least one synchronization pulse signal, and to provide the at least one synchronization pulse signal to each transceiver IC;
• and
• a plurality of clock buffer circuits coupled to the beamformer processor via a clock distribution circuit, wherein the plurality of clock buffer circuits are configured to output a plurality of clock signals, and to provide a respective clock signal to each transceiver IC, and wherein each transceiver IC is configured to:
• receive the respective clock signal and the at least one synchronization pulse signal;
• synchronize the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal;
• generate a carrier frequency signal using a phase-locked loop (PLL) circuit that includes a delta-sigma modulator (DSM) circuit;
• and
• use the generated carrier frequency signal to process frequency domain IQ data.