Split-dithering scheme in successive approximation analog to digital converter

A system, comprising:

• a first digital to analog converter (DAC) having a bit range;
• an analog to digital converter (ADC);
• a dither generator module that comprises:
• a most significant bits (MSB) dither generator device configured to generate a first integer random value with a magnitude having non-zero bits that are limited to a first number of bits in an MSB segment that comprises a first portion of an upper half of the bit range;
• and
• a least significant bit (LSB) dither generator device configured to generate a second integer random value with a magnitude having non-zero bits that are limited to a second number of bits in an LSB segment that comprises a second portion of a lower half of the bit range, wherein:
• the first DAC is configured to receive the first integer random value and the second integer random value and to generate a dither signal based on a sum of the first integer random value and the second integer random value;
• and
• the ADC is configured to receive a sum of the dither signal and a sampled input signal and generate a first digitized signal;
• and
• a subtraction module configured to subtract the sum of the first integer random value and the second integer random value from the first digitized signal to produce a digitized output signal.

A system, comprising:

• a digital to analog converter (DAC) having a bit range;
• an analog to digital converter (ADC);
• a most significant bits (MSB) dither generator device configured to generate a first integer random value, wherein a magnitude of the first integer random value has non-zero bits that are limited to an MSB segment of the bit range, wherein:
• the DAC is configured to receive the first integer random value and to generate a dither signal based on the first integer random value;
• and
• the ADC is configured to receive a sum of the dither signal and a sampled input signal and generate a first digitized signal.