Semiconductor device package die stacking system and method

A semiconductor device package comprising:

• a control die;
• a first die stack comprising a first plurality of semiconductor dies stacked one upon another, each die of the first plurality of semiconductor dies including a first edge and an opposing second edge;
• a first die bond wire electrically connected to and physically contacting each die of the first plurality of semiconductor dies;
• a first vertical bond wire connected to a first semiconductor die of the first plurality of semiconductor dies at the first edge of the first semiconductor die, the first vertical bond wire configured to electrically couple the first plurality of semiconductor dies to the control die;
• and
• a first encapsulant at least partially encapsulating the first plurality of semiconductor dies, the first die bond wire, and the first vertical bond wire, the first encapsulant having a top planar surface extending across an entire top surface of a topmost die of the first die stack;
• a second die stack comprising a second plurality of semiconductor dies, the second die stack having a bottommost surface directly contacting the top planar surface of the first encapsulant, each die of the second plurality of semiconductor dies stacked one upon another and including a first edge and an opposing second edge;
• a second die bond wire electrically connected to and physically contacting each die of the second plurality of semiconductor dies;
• a second vertical bond wire connected to a second semiconductor die of the second plurality of semiconductor dies at the first edge thereof, the second vertical bond wire configured to electrically couple the second plurality of semiconductor dies to the control die;
• a first extension to the first vertical bond wire directly connected to an end of the first vertical bond wire and extending upwardly from the top planar surface of the first encapsulant, the first extension to the first vertical bond wire being vertically aligned with the first vertical bond wire;
• a second encapsulant directly contacting the top planar surface of the first encapsulant and at least partially encapsulating the second plurality of semiconductor dies, the second die bond wire, and the second vertical bond wire;
• and
• a redistribution layer configured to electrically couple the control die to the first and second pluralities of semiconductor dies,
• wherein the control die, the first vertical bond wire and the second vertical bond wire are electrically connected to the redistribution layer,
• wherein the first extension to the first vertical bond wire and the second vertical bond wire are positioned on a same side of the second die stack, and
• wherein the first edge of each die of the first plurality of semiconductor dies is laterally closer to the first vertical bond wire than the respective second edge, and a lateral distance between each of the first edges of the first plurality of semiconductor dies and the first vertical bond wire increases as a vertical stacking distance of each die of the first plurality of semiconductor dies increases from a bottom surface of the first die stack,
• wherein the first edge of each die of the second plurality of semiconductor dies is laterally closer to the first vertical bond wire and the second vertical bond wire than the respective second edge, and
• wherein the first edge of one semiconductor die of the second plurality of semiconductor dies is positioned between the first edges of two semiconductor dies of the first plurality of semiconductor dies.