Random access memory and sense-amplifying compensation circuit thereof

A sense-amplifying (SA) compensation circuit, applied in a random access memory (RAM), comprising:

• a SA module, connected between a target bit line and a complementary bit line, and connected to SA voltage lines;
• wherein, in a charge sharing stage, the target bit line shares storage charges stored in a corresponding turned-on memory cell;
• and in a sensing stage, the SA module is configured to pull a target bit-line voltage of the target bit line, which has shared the storage charges, to one of a first SA voltage and a second SA voltage, and is configured to pull a complementary bit-line voltage of the complementary bit line, to the other of the first SA voltage and the second SA voltage;
• an offset cancellation module, connected between the target bit line and the SA module, and connected between the complementary bit line and the SA module, and is configured to perform an offset cancellation operation in an offset cancellation stage, for generating an offset cancellation voltage between the target bit line and the complementary bit line;
• and
• a drive module, configured to be connected to the SA voltage lines and is configured to drive the SA voltage lines to a state of the first SA voltage and the second SA voltage in the offset cancellation stage and the sensing stage;
• wherein the drive module is an adjustable drive module and is configured to drive the SA voltage lines in an adjustable manner during the offset cancellation stage, to adjust driving capabilities of the SA voltage lines to perform the offset cancellation operation.