Scanning signal line drive circuit and display device

A display device comprising:

• a scanning signal line drive circuit configured to drive a plurality of scanning signal lines, each connected to a plurality of pixel forming portions,
• wherein the scanning signal line drive circuit includes a shift register having a plurality of stages corresponding to the plurality of scanning signal lines on a one-to-one basis and configured to operate based on a plurality of first clock signals and a plurality of second clock signals, each of the plurality of second clock signals having an amplitude that is greater than an amplitude of each of the plurality of first clock signals,
• wherein a first unit circuit, among a plurality of unit circuits, that forms one of the plurality of stages included in the shift register includes:
• a first output node configured to output a control signal for controlling an operation performed by a second unit circuit of the plurality of unit circuits,
• a second output node configured to output a scanning signal to a corresponding one of the plurality of scanning signal lines.
• a first control node configured to change from an off level to an on level based on a control signal output from a first output node of a third unit circuit of the plurality of unit circuits that forms a preceding stage,
• a first output control transistor including a control terminal connected to the first control node, a first conduction terminal to which a corresponding one of the plurality of first clock signals is given, and a second conduction terminal connected to the first output node, and
• a second output control transistor including a control terminal connected to the first control node, a first conduction terminal to which a corresponding one of the plurality of second clock signals is given, and a second conduction terminal connected to the second output node,
• wherein a breakdown voltage of the second output control transistor is higher than a breakdown voltage of the first output control transistor,
• wherein the first output control transistor is composed of P transistors connected in series, where P is an integer greater than or equal to 2, and
• wherein the second output control transistor is composed of Q transistors connected in series, where Q is an integer greater than P.

A display device comprising:

• a scanning signal line drive circuit configured to drive a plurality of scanning signal lines, each connected to a plurality of pixel forming portions,
• wherein the scanning signal line drive circuit includes a shift register having a plurality of stages corresponding to the plurality of scanning signal lines on a one-to-one basis and configured to operate based on a plurality of first clock signals and a plurality of second clock signals, each of the plurality of second clock signals having an amplitude that is greater than an amplitude of each of the plurality of first clock signals,
• wherein a first unit circuit, among a plurality of unit circuits, that forms one of the plurality of stages included in the shift register includes:
• a first output node configured to output a control signal for controlling an operation performed by a second unit circuit of the plurality of unit circuits,
• a second output node configured to output a scanning signal to a corresponding one of the plurality of scanning signal lines,
• a first control node configured to change from an off level to an on level based on a control signal output from a first output node of a third unit circuit of the plurality of unit circuits that forms a preceding stage,
• a first output control transistor including a control terminal connected to the first control node, a first conduction terminal to which a corresponding one of the plurality of first clock signals is given, and a second conduction terminal connected to the first output node, and
• a second output control transistor including a control terminal connected to the first control node, a first conduction terminal to which a corresponding one of the plurality of second clock signals is given, and a second conduction terminal connected to the second output node,
• wherein a breakdown voltage of the second output control transistor is higher than a breakdown voltage of the first output control transistor,
• wherein one of the first conduction terminal and the second conduction terminal of the second output control transistor includes a first electrode portion provided at one end in a channel length direction of the second output control transistor and a second electrode portion provided at anotherend in the channel length direction of the second output control transistor and electrically connected to the first electrode portion, and
• wherein another one of the first conduction terminal and the second conduction terminal of the second output control transistor includes a third electrode portion provided between the first electrode portion and the second electrode portion so that a channel is formed between the third electrode portion and the first electrode portion and between the third electrode portion and the second electrode portion.