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US 12,346,603 B2Granted
Interface read after write
AssigneeMicron Technology, Inc.
InventorYue Chan
Life of this patent
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Abstract
An interface of a memory sub-system can receive a write command addressed to a first address and a read command addressed to a second address and can receive data corresponding to the write command. The interface can determine whether the first address matches the second address responsive to determining that the first address matches the second address, can drop the read command and the second address, and can provide the data to a host.
Claims20
A memory sub-system comprising:
- a memory device;
- a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device;
- and
- an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to:
- receive a write command addressed to a first address, a read command addressed to a second address from a host, and data corresponding to the write command from the host;
- responsive to determining that the first address matches the second address and that the write command was inserted into a command buffer of the interface prior to inserting the read command into the command buffer:
- drop the read command and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry;
- and
- provide the data to the host from a read buffer of the interface.
6 more elements
A method comprising:
- receiving, at an interface of a memory sub-system and from a host, a write command addressed to a first address and a read command addressed to a second address;
- storing the write command and the read command in a command buffer of the interface;
- determining, using a comparator of the interface, whether the first address matches the second address;
- determining whether data stored in a write buffer of the interface and corresponding to the write command is corrupt;
- responsive to determining that the first address matches the second address, and that the data is not corrupt:
- dropping, at the interface, the read command and the second address from the command buffer by sending a signal from the comparator to error correction circuitry of the interface to cause the error correction circuitry to mark the read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the read command responsive to the read command being marked by the error correction circuitry;
- and
- providing the data to the host from a read buffer of the interface;
- and
- responsive to determining that the first address does not match the second address or that the data is corrupt, providing the read command and the second address to a processing device coupled to a memory device of the memory sub-system and configured to control cache memory for the memory device to store data prior to storing the data on the memory device.
7 more elements
A memory sub-system, comprising:
- a memory device;
- a processing device coupled to the memory device and configured to control cache memory for the memory device to store data prior to storing the data on the memory device;
- and
- an interface of the memory sub-system comprising error correction circuitry and a comparator, wherein the interface is coupled to the processing device and configured to:
- receive a write command addressed to a first address, a first read command and a second read command addressed to a second address from a host, and data corresponding to the write command from the host;
- responsive to determining that the first address matches the second address and that the data is not corrupt:
- drop the first read command, the second read command, and the second address from the command buffer by sending a signal from the comparator to the error correction circuitry to cause the error correction circuitry to mark the first read command and the second read command as being erroneous without regard to performing an error check on the read command and without regard to whether the read command passes an error check if performed, wherein a memory sub-system controller is configured to delete the first read command and the second read command responsive to the first read command and the second read command being marked by the error correction circuitry;
- and
- provide the data to the host from a read buffer of the interface;
- and
- responsive to determining that the first address does not match the second address or that the data is corrupt, provide the first read command, the second read command, and the second address to the processing device for processing.
8 more elements
Dependencies are inferred from the claim text.