Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA
AssigneeIntel Corporation
InventorsAlpa Trivedi, Scott Weber, Steffen Schulz, Patrick Koeberl
Life of this patent
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AssigneeIntel Corporation
InventorsAlpa Trivedi, Scott Weber, Steffen Schulz, Patrick Koeberl
Estimating the term…
An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to perform, as part of a PR configuration sequence for a new partial reconfiguration (PR) persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation.
An apparatus comprising:
A method comprising:
A non-transitory machine-readable storage medium comprising instructions that, when executed, cause at least one processor to at least:
Dependencies are inferred from the claim text.