Clock recovery circuit, error rate measurement apparatus, and error rate measurement method

A clock recovery circuit comprising:

• a reference clock generation unit that generates a reference clock subjected to spread spectrum clock (SSC) modulation;
• a clock recovery unit that recovers an SSC modulated clock of a data signal subjected to the SSC modulation at a predetermined SSC modulated frequency in synchronization with the reference clock;
• a frequency modulation (FM) demodulation unit that performs FM demodulation on the SSC modulated clock recovered by the clock recovery unit to generate an FM demodulated signal;
• and
• a modulation signal generation unit that acquires cycle information indicating a cycle of the FM demodulated signal and slope information indicating a slope of the FM demodulated signal to generate a modulation signal based on the acquired cycle information and slope information,
• wherein the reference clock generation unit includes
• a voltage-controlled oscillator that outputs an output signal of a frequency corresponding to an input control voltage,
• a phase comparator that outputs a phase difference signal corresponding to a phase difference between a base clock having a predetermined frequency and the output signal of the voltage-controlled oscillator,
• a charge pump that generates a charge/discharge current in response to the phase difference signal,
• a loop filter that outputs a signal obtained by removing a high frequency component from the charge/discharge current, and
• a signal synthesis unit that adds the modulation signal generated by the modulation signal generation unit and the output of the loop filter, and
• the voltage-controlled oscillator generates the reference clock by modulating a clock of the voltage-controlled oscillator by receiving the output of the signal synthesis unit as the control voltage, to output the generated reference clock as the output signal.