Computing system for mitigating execution drift

At least one non-transitory machine readable storage medium having instructions stored thereon, the instructions, when executed by a machine, cause the machine to:

• execute, by a first processor core, a first instance of an application;
• execute, by a second processor core, a second instance of the application concurrently with the execution of the first instance of the application by the first processor core,
• wherein the first processor core and the second processor core are part of the same system on a chip (SoC) and form a workload pair that independently execute the first instance of the application and the second instance of the application, the second instance of the application comprising a duplication of the first instance of the application;
• direct an interrupt to the first processor core based on an indication that an execution state of the first processor core is ahead of an execution state of the second processor core to thereby assign processing of the interrupt to a leading processing core from among the first processor core and the second processor core;
• store an indication of one or more leading processor cores;
• and
• store respective weights for one or more leading processor cores, the weights defining a relative frequency with which each of the one or more leading processor cores is to receive interrupts redirected from one or more lagging processor cores.

A method comprising:

• executing, by a first processor core, a first instance of an application;
• executing, by a second processor core, a second instance of the application concurrently with the execution of the first instance of the application by the first processor core,
• wherein the first processor core and the second processor core are part of the same system on a chip (SoC) and form a workload pair that independently execute the first instance of the application and the second instance of the application, the second instance of the application comprising a duplication of the first instance of the application;
• directing an interrupt to the first processor core based on an indication that an execution state of the first processor core is ahead of an execution state of the second processor core to thereby assign processing of the interrupt to a leading processing core from among the first processor core and the second processor core;
• storing an indication of one or more leading processor cores;
• and
• storing respective weights for one or more leading processor cores, the weights defining a relative frequency with which each of the one or more leading processor cores is to receive interrupts redirected from one or more lagging processor cores.