Semiconductor storage device

A semiconductor storage device comprising:

• a memory cell array;
• and
• a peripheral circuit disposed at least partially below the memory cell array,
• wherein the peripheral circuit includes an RC circuit in which a resistive portion and a capacitive portion are electrically connected to each other in series,
• wherein the resistive portion includes:
• first and second lower conductors at a level that is below the memory cell array;
• an upper conductor at a level that is above the memory cell array;
• a first contact that extends upward from the first lower conductor, and connects the first lower conductor to the upper conductor;
• and
• a second contact that extends downward from the upper conductor, and connects the upper conductor to the second lower conductor, and
• wherein the first lower conductor, the first contact, the upper conductor, the second contact, and the second lower conductor are electrically connected in series in this order and the first lower conductor is closest to the capacitive portion along a current path formed by the capacitive portion and the resistive portion.